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20 | 20 |
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21 | 21 | #if defined(__SSE2__) |
22 | 22 | #define LIBC_TARGET_CPU_HAS_SSE2 |
| 23 | +#define LIBC_TARGET_CPU_HAS_FPU_FLOAT |
| 24 | +#define LIBC_TARGET_CPU_HAS_FPU_DOUBLE |
23 | 25 | #endif |
24 | 26 |
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25 | 27 | #if defined(__SSE4_2__) |
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42 | 44 | #define LIBC_TARGET_CPU_HAS_AVX512BW |
43 | 45 | #endif |
44 | 46 |
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| 47 | +#if defined(__ARM_FP) |
| 48 | +#if (__ARM_FP & 0x2) |
| 49 | +#define LIBC_TARGET_CPU_HAS_ARM_FPU_HALF |
| 50 | +#define LIBC_TARGET_CPU_HAS_FPU_HALF |
| 51 | +#endif // LIBC_TARGET_CPU_HAS_ARM_FPU_HALF |
| 52 | +#if (__ARM_FP & 0x4) |
| 53 | +#define LIBC_TARGET_CPU_HAS_ARM_FPU_FLOAT |
| 54 | +#define LIBC_TARGET_CPU_HAS_FPU_FLOAT |
| 55 | +#endif // LIBC_TARGET_CPU_HAS_ARM_FPU_FLOAT |
| 56 | +#if (__ARM_FP & 0x8) |
| 57 | +#define LIBC_TARGET_CPU_HAS_ARM_FPU_DOUBLE |
| 58 | +#define LIBC_TARGET_CPU_HAS_FPU_DOUBLE |
| 59 | +#endif // LIBC_TARGET_CPU_HAS_ARM_FPU_DOUBLE |
| 60 | +#endif // __ARM_FP |
| 61 | + |
| 62 | +#if defined(__riscv_flen) |
| 63 | +// https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc |
| 64 | +#if (__riscv_flen & 0x10) |
| 65 | +#define LIBC_TARGET_CPU_HAS_RISCV_FPU_HALF |
| 66 | +#define LIBC_TARGET_CPU_HAS_FPU_HALF |
| 67 | +#endif // LIBC_TARGET_CPU_HAS_RISCV_FPU_HALF |
| 68 | +#if (__riscv_flen & 0x20) |
| 69 | +#define LIBC_TARGET_CPU_HAS_RISCV_FPU_FLOAT |
| 70 | +#define LIBC_TARGET_CPU_HAS_FPU_FLOAT |
| 71 | +#endif // LIBC_TARGET_CPU_HAS_RISCV_FPU_FLOAT |
| 72 | +#if (__riscv_flen & 0x40) |
| 73 | +#define LIBC_TARGET_CPU_HAS_RISCV_FPU_DOUBLE |
| 74 | +#define LIBC_TARGET_CPU_HAS_FPU_DOUBLE |
| 75 | +#endif // LIBC_TARGET_CPU_HAS_RISCV_FPU_DOUBLE |
| 76 | +#endif // __riscv_flen |
| 77 | + |
| 78 | +#if defined(__NVPTX__) || defined(__AMDGPU__) |
| 79 | +#define LIBC_TARGET_CPU_HAS_FPU_FLOAT |
| 80 | +#define LIBC_TARGET_CPU_HAS_FPU_DOUBLE |
| 81 | +#endif |
| 82 | + |
45 | 83 | #if defined(__ARM_FEATURE_FMA) || (defined(__AVX2__) && defined(__FMA__)) || \ |
46 | 84 | defined(__NVPTX__) || defined(__AMDGPU__) || defined(__LIBC_RISCV_USE_FMA) |
47 | 85 | #define LIBC_TARGET_CPU_HAS_FMA |
48 | 86 | // Provide a more fine-grained control of FMA instruction for ARM targets. |
49 | | -#if defined(__ARM_FP) |
50 | | -#if (__ARM_FP & 0x2) |
| 87 | +#if defined(LIBC_TARGET_CPU_HAS_FPU_HALF) |
51 | 88 | #define LIBC_TARGET_CPU_HAS_FMA_HALF |
52 | 89 | #endif // LIBC_TARGET_CPU_HAS_FMA_HALF |
53 | | -#if (__ARM_FP & 0x4) |
| 90 | +#if defined(LIBC_TARGET_CPU_HAS_FPU_FLOAT) |
54 | 91 | #define LIBC_TARGET_CPU_HAS_FMA_FLOAT |
55 | 92 | #endif // LIBC_TARGET_CPU_HAS_FMA_FLOAT |
56 | | -#if (__ARM_FP & 0x8) |
| 93 | +#if defined(LIBC_TARGET_CPU_HAS_FPU_DOUBLE) |
57 | 94 | #define LIBC_TARGET_CPU_HAS_FMA_DOUBLE |
58 | 95 | #endif // LIBC_TARGET_CPU_HAS_FMA_DOUBLE |
59 | | -#else |
60 | | -#define LIBC_TARGET_CPU_HAS_FMA_FLOAT |
61 | | -#define LIBC_TARGET_CPU_HAS_FMA_DOUBLE |
62 | | -#endif |
63 | 96 | #endif |
64 | 97 |
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65 | 98 | #if defined(LIBC_TARGET_ARCH_IS_AARCH64) || \ |
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