Tidy up and add tests with frame-ptr attr

Author: rovka

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

@@ -714,8 +714,6 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
     assert(hasFP(MF));
     Register FPReg = MFI->getFrameOffsetReg();
     assert(FPReg != AMDGPU::FP_REG);
-    Register SPReg = MFI->getStackPtrOffsetReg();
-    assert(SPReg != AMDGPU::SP_REG);
     unsigned VGPRSize =
         llvm::alignTo((ST.getAddressableNumVGPRs() -
                        AMDGPU::IsaInfo::getVGPRAllocGranule(&ST)) *
@@ -732,6 +730,9 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
     BuildMI(MBB, I, DL, TII->get(AMDGPU::S_CMP_LG_U32)).addImm(0).addReg(FPReg);
     BuildMI(MBB, I, DL, TII->get(AMDGPU::S_CMOVK_I32), FPReg).addImm(VGPRSize);
     if (requiresStackPointerReference(MF)) {
+      Register SPReg = MFI->getStackPtrOffsetReg();
+      assert(SPReg != AMDGPU::SP_REG);
+
       // If at least one of the constants can be inlined, then we can use
       // s_cselect. Otherwise, use a mov and cmovk.
       if (AMDGPU::isInlinableLiteral32(Offset, ST.hasInv2PiInlineImm()) ||

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

@@ -512,13 +512,6 @@ Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const SIFrameLowering *TFI = ST.getFrameLowering();
   const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
 
-  // If we need to reserve scratch space for saving the VGPRs, then we should
-  // use the frame register for accessing our own frame (which may start at a
-  // non-zero offset).
-  if (TFI->mayReserveScratchForCWSR(MF))
-    return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg()
-                          : FuncInfo->getStackPtrOffsetReg();
-
   // During ISel lowering we always reserve the stack pointer in entry and chain
   // functions, but never actually want to reference it when accessing our own
   // frame. If we need a frame pointer we use it, but otherwise we can just use

llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll

@@ -134,6 +134,38 @@ define amdgpu_cs void @realign_stack(<32 x i32> %x) #0 {
   ret void
 }
 
+define amdgpu_cs void @frame_pointer_none() #1 {
+; CHECK-LABEL: frame_pointer_none:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
+; CHECK-NEXT:    v_mov_b32_e32 v0, 13
+; CHECK-NEXT:    s_cmp_lg_u32 0, s33
+; CHECK-NEXT:    s_cmovk_i32 s33, 0x1c0
+; CHECK-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-NEXT:    s_wait_storecnt 0x0
+; CHECK-NEXT:    s_alloc_vgpr 0
+; CHECK-NEXT:    s_endpgm
+  %local = alloca i32, addrspace(5)
+  store volatile i8 13, ptr addrspace(5) %local
+  ret void
+}
+
+define amdgpu_cs void @frame_pointer_all() #2 {
+; CHECK-LABEL: frame_pointer_all:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
+; CHECK-NEXT:    v_mov_b32_e32 v0, 13
+; CHECK-NEXT:    s_cmp_lg_u32 0, s33
+; CHECK-NEXT:    s_cmovk_i32 s33, 0x1c0
+; CHECK-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-NEXT:    s_wait_storecnt 0x0
+; CHECK-NEXT:    s_alloc_vgpr 0
+; CHECK-NEXT:    s_endpgm
+  %local = alloca i32, addrspace(5)
+  store volatile i8 13, ptr addrspace(5) %local
+  ret void
+}
+
 ; Non-entry functions and graphics shaders don't need to worry about CWSR.
 define amdgpu_gs void @amdgpu_gs() #0 {
 ; CHECK-LABEL: amdgpu_gs:
@@ -215,3 +247,5 @@ define void @default() #0 {
 declare amdgpu_gfx void @callee(i32) #0
 
 attributes #0 = { nounwind }
+attributes #1 = { nounwind "frame-pointer"="none" }
+attributes #2 = { nounwind "frame-pointer"="all" }