fixup! determine when DT and MLI need to be recalculated

Author: michaelmaitland

llvm/lib/CodeGen/PeepholeOptimizer.cpp

@@ -433,6 +433,8 @@ class PeepholeOptimizer : private MachineFunction::Delegate {
   MachineDominatorTree *DT = nullptr; // Machine dominator tree
   MachineLoopInfo *MLI = nullptr;
 
+  bool NeedToInvalidateMLI = false;
+
 public:
   PeepholeOptimizer(MachineDominatorTree *DT, MachineLoopInfo *MLI)
       : DT(DT), MLI(MLI) {}
@@ -444,6 +446,7 @@ class PeepholeOptimizer : private MachineFunction::Delegate {
   /// Sequence of instructions that formulate recurrence cycle.
   using RecurrenceCycle = SmallVector<RecurrenceInstr, 4>;
 
+  bool needToInvalidateMLI() const { return NeedToInvalidateMLI; }
 private:
   bool optimizeCmpInstr(MachineInstr &MI);
   bool optimizeExtInstr(MachineInstr &MI, MachineBasicBlock &MBB,
@@ -568,8 +571,10 @@ class PeepholeOptimizerLegacy : public MachineFunctionPass {
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     MachineFunctionPass::getAnalysisUsage(AU);
     AU.addRequired<MachineLoopInfoWrapperPass>();
-    if (Aggressive)
+    if (Aggressive) {
       AU.addRequired<MachineDominatorTreeWrapperPass>();
+      AU.addPreserved<MachineDominatorTreeWrapperPass>();
+    }
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
@@ -1654,7 +1659,13 @@ PeepholeOptimizerPass::run(MachineFunction &MF,
   if (!Changed)
     return PreservedAnalyses::all();
 
-  return getMachineFunctionPassPreservedAnalyses();
+  auto PA = getMachineFunctionPassPreservedAnalyses();
+  PA.preserve<MachineDominatorTreeAnalysis>();
+  if (!Impl.needToInvalidateMLI()) {
+    PA.preserve<MachineLoopAnalysis>();
+    PA.preserveSet<CFGAnalyses>();
+  }
+  return PA;
 }
 
 bool PeepholeOptimizerLegacy::runOnMachineFunction(MachineFunction &MF) {
@@ -1783,17 +1794,21 @@ bool PeepholeOptimizer::run(MachineFunction &MF) {
       }
 
       if (MI->isConditionalBranch() && optimizeCondBranch(*MI)) {
+        NeedToInvalidateMLI = true;
         // optimizeCondBranch might have converted a conditional branch to
         // an unconditional branch. If there is a branch instruction after it,
         // delete it.
         MachineInstr *NewBr = &*std::prev(MII);
         if (NewBr->isUnconditionalBranch()) {
           if (MII != MBB.end()) {
             MachineInstr *Dead = &*MII;
-            ++MII;
             MachineBasicBlock *DeadDest = TII->getBranchDestBlock(*Dead);
-            if (DT && TII->getBranchDestBlock(*NewBr) != DeadDest)
+            if (DT && TII->getBranchDestBlock(*NewBr) != DeadDest) {
               DT->deleteEdge(&MBB, DeadDest);
+              MLI->calculate(*DT);
+              NeedToInvalidateMLI = false;
+            }
+            ++MII;
             Dead->eraseFromParent();
           }
         }

llvm/test/CodeGen/AArch64/O3-pipeline.ll

@@ -160,6 +160,8 @@
 ; CHECK-NEXT:       Machine code sinking
 ; CHECK-NEXT:       Peephole Optimizations
 ; CHECK-NEXT:       Remove dead machine instructions
+; CHECK-NEXT:       MachineDominator Tree Construction
+; CHECK-NEXT:       Machine Natural Loop Construction
 ; CHECK-NEXT:       AArch64 MI Peephole Optimization pass
 ; CHECK-NEXT:       AArch64 Dead register definitions
 ; CHECK-NEXT:       Detect Dead Lanes
@@ -169,7 +171,6 @@
 ; CHECK-NEXT:       Live Variable Analysis
 ; CHECK-NEXT:       Eliminate PHI nodes for register allocation
 ; CHECK-NEXT:       Two-Address instruction pass
-; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       Slot index numbering
 ; CHECK-NEXT:       Live Interval Analysis
 ; CHECK-NEXT:       Register Coalescer

llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

@@ -343,6 +343,7 @@
 ; GCN-O1-NEXT:        Remove unreachable machine basic blocks
 ; GCN-O1-NEXT:        Live Variable Analysis
 ; GCN-O1-NEXT:        MachineDominator Tree Construction
+; GCN-O1-NEXT:        Machine Natural Loop Construction
 ; GCN-O1-NEXT:        SI Optimize VGPR LiveRange
 ; GCN-O1-NEXT:        Eliminate PHI nodes for register allocation
 ; GCN-O1-NEXT:        SI Lower control flow pseudo instructions
@@ -639,8 +640,9 @@
 ; GCN-O1-OPTS-NEXT:        GCN DPP Combine
 ; GCN-O1-OPTS-NEXT:        SI Load Store Optimizer
 ; GCN-O1-OPTS-NEXT:        SI Peephole SDWA
-; GCN-O1-OPTS-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-OPTS-NEXT:        MachineDominator Tree Construction
+; GCN-O1-OPTS-NEXT:        Machine Natural Loop Construction
+; GCN-O1-OPTS-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-OPTS-NEXT:        Early Machine Loop Invariant Code Motion
 ; GCN-O1-OPTS-NEXT:        MachineDominator Tree Construction
 ; GCN-O1-OPTS-NEXT:        Machine Block Frequency Analysis
@@ -957,8 +959,9 @@
 ; GCN-O2-NEXT:        GCN DPP Combine
 ; GCN-O2-NEXT:        SI Load Store Optimizer
 ; GCN-O2-NEXT:        SI Peephole SDWA
-; GCN-O2-NEXT:        Machine Block Frequency Analysis
 ; GCN-O2-NEXT:        MachineDominator Tree Construction
+; GCN-O2-NEXT:        Machine Natural Loop Construction
+; GCN-O2-NEXT:        Machine Block Frequency Analysis
 ; GCN-O2-NEXT:        Early Machine Loop Invariant Code Motion
 ; GCN-O2-NEXT:        MachineDominator Tree Construction
 ; GCN-O2-NEXT:        Machine Block Frequency Analysis
@@ -1289,8 +1292,9 @@
 ; GCN-O3-NEXT:        GCN DPP Combine
 ; GCN-O3-NEXT:        SI Load Store Optimizer
 ; GCN-O3-NEXT:        SI Peephole SDWA
-; GCN-O3-NEXT:        Machine Block Frequency Analysis
 ; GCN-O3-NEXT:        MachineDominator Tree Construction
+; GCN-O3-NEXT:        Machine Natural Loop Construction
+; GCN-O3-NEXT:        Machine Block Frequency Analysis
 ; GCN-O3-NEXT:        Early Machine Loop Invariant Code Motion
 ; GCN-O3-NEXT:        MachineDominator Tree Construction
 ; GCN-O3-NEXT:        Machine Block Frequency Analysis

llvm/test/CodeGen/ARM/O3-pipeline.ll

@@ -104,6 +104,7 @@
 ; CHECK-NEXT:      Peephole Optimizations
 ; CHECK-NEXT:      Remove dead machine instructions
 ; CHECK-NEXT:      MachineDominator Tree Construction
+; CHECK-NEXT:      Machine Natural Loop Construction
 ; CHECK-NEXT:      Slot index numbering
 ; CHECK-NEXT:      Live Interval Analysis
 ; CHECK-NEXT:      Lazy Machine Block Frequency Analysis

llvm/test/CodeGen/LoongArch/opt-pipeline.ll

@@ -116,9 +116,10 @@
 ; LAXX-NEXT:       Process Implicit Definitions
 ; LAXX-NEXT:       Remove unreachable machine basic blocks
 ; LAXX-NEXT:       Live Variable Analysis
+; LAXX-NEXT:       MachineDominator Tree Construction
+; LAXX-NEXT:       Machine Natural Loop Construction
 ; LAXX-NEXT:       Eliminate PHI nodes for register allocation
 ; LAXX-NEXT:       Two-Address instruction pass
-; LAXX-NEXT:       MachineDominator Tree Construction
 ; LAXX-NEXT:       Slot index numbering
 ; LAXX-NEXT:       Live Interval Analysis
 ; LAXX-NEXT:       Register Coalescer

llvm/test/CodeGen/RISCV/O3-pipeline.ll

@@ -117,13 +117,14 @@
 ; CHECK-NEXT:       Machine code sinking
 ; CHECK-NEXT:       Peephole Optimizations
 ; CHECK-NEXT:       Remove dead machine instructions
+; CHECK-NEXT:       MachineDominator Tree Construction
+; CHECK-NEXT:       Machine Natural Loop Construction
 ; CHECK-NEXT:       Machine Trace Metrics
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine InstCombiner
 ; RV64-NEXT:        RISC-V Optimize W Instructions
 ; CHECK-NEXT:       RISC-V Pre-RA pseudo instruction expansion pass
 ; CHECK-NEXT:       RISC-V Merge Base Offset
-; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       RISC-V VL Optimizer
 ; CHECK-NEXT:       RISC-V Insert Read/Write CSR Pass
 ; CHECK-NEXT:       RISC-V Insert Write VXRM Pass