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spallspall
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make clang format happy
1 parent 72b3aaa commit d080a9b

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3 files changed

+71
-69
lines changed

3 files changed

+71
-69
lines changed

‎clang/lib/CodeGen/CGBuiltin.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18870,7 +18870,7 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID,
1887018870
Value *X = EmitScalarExpr(E->getArg(0));
1887118871

1887218872
return Builder.CreateIntrinsic(
18873-
/*ReturnType=*/ConvertType(E->getType()),
18873+
/*ReturnType=*/ConvertType(E->getType()),
1887418874
getFirstBitHighIntrinsic(CGM.getHLSLRuntime(), E->getArg(0)->getType()),
1887518875
ArrayRef<Value *>{X}, nullptr, "hlsl.firstbithigh");
1887618876
}

‎clang/lib/Sema/SemaHLSL.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1959,7 +1959,8 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
19591959

19601960
if (auto *VecTy = EltTy->getAs<VectorType>()) {
19611961
EltTy = VecTy->getElementType();
1962-
ResTy = SemaRef.Context.getVectorType(ResTy, VecTy->getNumElements(), VecTy->getVectorKind());
1962+
ResTy = SemaRef.Context.getVectorType(ResTy, VecTy->getNumElements(),
1963+
VecTy->getVectorKind());
19631964
}
19641965

19651966
if (!EltTy->isIntegerType()) {

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

Lines changed: 68 additions & 67 deletions
Original file line numberDiff line numberDiff line change
@@ -93,24 +93,24 @@ class SPIRVInstructionSelector : public InstructionSelector {
9393
MachineInstr &I) const;
9494

9595
bool selectFirstBitHigh(Register ResVReg, const SPIRVType *ResType,
96-
MachineInstr &I, bool IsSigned) const;
96+
MachineInstr &I, bool IsSigned) const;
9797

9898
bool selectFirstBitHigh16(Register ResVReg, const SPIRVType *ResType,
99-
MachineInstr &I, bool IsSigned) const;
99+
MachineInstr &I, bool IsSigned) const;
100100

101101
bool selectFirstBitHigh32(Register ResVReg, const SPIRVType *ResType,
102-
MachineInstr &I, Register SrcReg,
103-
bool IsSigned) const;
102+
MachineInstr &I, Register SrcReg,
103+
bool IsSigned) const;
104104

105105
bool selectFirstBitHigh64(Register ResVReg, const SPIRVType *ResType,
106-
MachineInstr &I, bool IsSigned) const;
106+
MachineInstr &I, bool IsSigned) const;
107107

108108
bool selectGlobalValue(Register ResVReg, MachineInstr &I,
109109
const MachineInstr *Init = nullptr) const;
110110

111111
bool selectNAryOpWithSrcs(Register ResVReg, const SPIRVType *ResType,
112-
MachineInstr &I, std::vector<Register> SrcRegs,
113-
unsigned Opcode) const;
112+
MachineInstr &I, std::vector<Register> SrcRegs,
113+
unsigned Opcode) const;
114114

115115
bool selectUnOpWithSrc(Register ResVReg, const SPIRVType *ResType,
116116
MachineInstr &I, Register SrcReg,
@@ -837,14 +837,14 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
837837
}
838838

839839
bool SPIRVInstructionSelector::selectNAryOpWithSrcs(Register ResVReg,
840-
const SPIRVType *ResType,
841-
MachineInstr &I,
842-
std::vector<Register> Srcs,
843-
unsigned Opcode) const {
840+
const SPIRVType *ResType,
841+
MachineInstr &I,
842+
std::vector<Register> Srcs,
843+
unsigned Opcode) const {
844844
auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
845-
.addDef(ResVReg)
846-
.addUse(GR.getSPIRVTypeID(ResType));
847-
for(Register SReg : Srcs) {
845+
.addDef(ResVReg)
846+
.addUse(GR.getSPIRVTypeID(ResType));
847+
for (Register SReg : Srcs) {
848848
MIB.addUse(SReg);
849849
}
850850
return MIB.constrainAllUses(TII, TRI, RBI);
@@ -2714,46 +2714,46 @@ Register SPIRVInstructionSelector::buildPointerToResource(
27142714
}
27152715

27162716
bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
2717-
const SPIRVType *ResType,
2718-
MachineInstr &I,
2719-
bool IsSigned) const {
2717+
const SPIRVType *ResType,
2718+
MachineInstr &I,
2719+
bool IsSigned) const {
27202720
unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert;
27212721
// zero or sign extend
27222722
Register ExtReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
2723-
bool Result = selectUnOpWithSrc(ExtReg, ResType, I, I.getOperand(2).getReg(),
2724-
Opcode);
2723+
bool Result =
2724+
selectUnOpWithSrc(ExtReg, ResType, I, I.getOperand(2).getReg(), Opcode);
27252725
return Result & selectFirstBitHigh32(ResVReg, ResType, I, ExtReg, IsSigned);
27262726
}
27272727

27282728
bool SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
2729-
const SPIRVType *ResType,
2730-
MachineInstr &I,
2731-
Register SrcReg,
2732-
bool IsSigned) const {
2729+
const SPIRVType *ResType,
2730+
MachineInstr &I,
2731+
Register SrcReg,
2732+
bool IsSigned) const {
27332733
unsigned Opcode = IsSigned ? GL::FindSMsb : GL::FindUMsb;
27342734
return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
2735-
.addDef(ResVReg)
2736-
.addUse(GR.getSPIRVTypeID(ResType))
2737-
.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
2738-
.addImm(Opcode)
2739-
.addUse(SrcReg)
2740-
.constrainAllUses(TII, TRI, RBI);
2735+
.addDef(ResVReg)
2736+
.addUse(GR.getSPIRVTypeID(ResType))
2737+
.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
2738+
.addImm(Opcode)
2739+
.addUse(SrcReg)
2740+
.constrainAllUses(TII, TRI, RBI);
27412741
}
27422742

27432743
bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
2744-
const SPIRVType *ResType,
2745-
MachineInstr &I,
2746-
bool IsSigned) const {
2744+
const SPIRVType *ResType,
2745+
MachineInstr &I,
2746+
bool IsSigned) const {
27472747
Register OpReg = I.getOperand(2).getReg();
27482748
// 1. split our int64 into 2 pieces using a bitcast
27492749
unsigned count = GR.getScalarOrVectorComponentCount(ResType);
27502750
SPIRVType *baseType = GR.retrieveScalarOrVectorIntType(ResType);
27512751
MachineIRBuilder MIRBuilder(I);
2752-
SPIRVType *postCastT = GR.getOrCreateSPIRVVectorType(baseType, 2 * count,
2753-
MIRBuilder);
2752+
SPIRVType *postCastT =
2753+
GR.getOrCreateSPIRVVectorType(baseType, 2 * count, MIRBuilder);
27542754
Register bitcastReg = MRI->createVirtualRegister(GR.getRegClass(postCastT));
2755-
bool Result = selectUnOpWithSrc(bitcastReg, postCastT, I, OpReg,
2756-
SPIRV::OpBitcast);
2755+
bool Result =
2756+
selectUnOpWithSrc(bitcastReg, postCastT, I, OpReg, SPIRV::OpBitcast);
27572757

27582758
// 2. call firstbithigh
27592759
Register FBHReg = MRI->createVirtualRegister(GR.getRegClass(postCastT));
@@ -2771,76 +2771,77 @@ bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
27712771
// count should be one.
27722772

27732773
Register HighReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
2774-
auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
2775-
TII.get(SPIRV::OpVectorShuffle))
2776-
.addDef(HighReg)
2777-
.addUse(GR.getSPIRVTypeID(VResType))
2778-
.addUse(FBHReg)
2779-
.addUse(FBHReg); // this vector will not be selected from; could be empty
2774+
auto MIB =
2775+
BuildMI(*I.getParent(), I, I.getDebugLoc(),
2776+
TII.get(SPIRV::OpVectorShuffle))
2777+
.addDef(HighReg)
2778+
.addUse(GR.getSPIRVTypeID(VResType))
2779+
.addUse(FBHReg)
2780+
.addUse(
2781+
FBHReg); // this vector will not be selected from; could be empty
27802782
unsigned i;
2781-
for(i = 0; i < count*2; i += 2) {
2783+
for (i = 0; i < count * 2; i += 2) {
27822784
MIB.addImm(i);
27832785
}
27842786
Result &= MIB.constrainAllUses(TII, TRI, RBI);
27852787

27862788
// get low bits
27872789
Register LowReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
2788-
MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
2789-
TII.get(SPIRV::OpVectorShuffle))
2790-
.addDef(LowReg)
2791-
.addUse(GR.getSPIRVTypeID(VResType))
2792-
.addUse(FBHReg)
2793-
.addUse(FBHReg); // this vector will not be selected from; could be empty
2794-
for(i = 1; i < count*2; i += 2) {
2790+
MIB =
2791+
BuildMI(*I.getParent(), I, I.getDebugLoc(),
2792+
TII.get(SPIRV::OpVectorShuffle))
2793+
.addDef(LowReg)
2794+
.addUse(GR.getSPIRVTypeID(VResType))
2795+
.addUse(FBHReg)
2796+
.addUse(
2797+
FBHReg); // this vector will not be selected from; could be empty
2798+
for (i = 1; i < count * 2; i += 2) {
27952799
MIB.addImm(i);
27962800
}
27972801
Result &= MIB.constrainAllUses(TII, TRI, RBI);
27982802

2799-
SPIRVType *BoolType =
2800-
GR.getOrCreateSPIRVVectorType(GR.getOrCreateSPIRVBoolType(I, TII),
2801-
count,
2802-
MIRBuilder);
2803+
SPIRVType *BoolType = GR.getOrCreateSPIRVVectorType(
2804+
GR.getOrCreateSPIRVBoolType(I, TII), count, MIRBuilder);
28032805
// check if the high bits are == -1;
28042806
Register NegOneReg = GR.getOrCreateConstVector(-1, I, VResType, TII);
28052807
// true if -1
28062808
Register BReg = MRI->createVirtualRegister(GR.getRegClass(BoolType));
28072809
Result &= selectNAryOpWithSrcs(BReg, BoolType, I, {HighReg, NegOneReg},
2808-
SPIRV::OpIEqual);
2810+
SPIRV::OpIEqual);
28092811

28102812
// Select low bits if true in BReg, otherwise high bits
28112813
Register TmpReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
28122814
Result &= selectNAryOpWithSrcs(TmpReg, VResType, I, {BReg, LowReg, HighReg},
2813-
SPIRV::OpSelectVIVCond);
2815+
SPIRV::OpSelectVIVCond);
28142816

28152817
// Add 32 for high bits, 0 for low bits
28162818
Register ValReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
28172819
bool ZeroAsNull = STI.isOpenCLEnv();
28182820
Register Reg32 = GR.getOrCreateConstVector(32, I, VResType, TII, ZeroAsNull);
28192821
Register Reg0 = GR.getOrCreateConstVector(0, I, VResType, TII, ZeroAsNull);
28202822
Result &= selectNAryOpWithSrcs(ValReg, VResType, I, {BReg, Reg0, Reg32},
2821-
SPIRV::OpSelectVIVCond);
2823+
SPIRV::OpSelectVIVCond);
28222824

28232825
Register AddReg = ResVReg;
2824-
if(isScalarRes)
2826+
if (isScalarRes)
28252827
AddReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
28262828
Result &= selectNAryOpWithSrcs(AddReg, VResType, I, {ValReg, TmpReg},
2827-
SPIRV::OpIAddV);
2829+
SPIRV::OpIAddV);
28282830

28292831
// convert result back to scalar if necessary
28302832
if (!isScalarRes)
28312833
return Result;
28322834
else
2833-
return Result & selectNAryOpWithSrcs(ResVReg, ResType, I,
2834-
{AddReg,
2835-
GR.getOrCreateConstInt(0, I, ResType,
2836-
TII)},
2837-
SPIRV::OpVectorExtractDynamic);
2835+
return Result & selectNAryOpWithSrcs(
2836+
ResVReg, ResType, I,
2837+
{AddReg, GR.getOrCreateConstInt(0, I, ResType, TII)},
2838+
SPIRV::OpVectorExtractDynamic);
28382839
}
28392840

28402841
bool SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
2841-
const SPIRVType *ResType,
2842-
MachineInstr &I,
2843-
bool IsSigned) const {
2842+
const SPIRVType *ResType,
2843+
MachineInstr &I,
2844+
bool IsSigned) const {
28442845
// FindUMsb intrinsic only supports 32 bit integers
28452846
Register OpReg = I.getOperand(2).getReg();
28462847
SPIRVType *OpType = GR.getSPIRVTypeForVReg(OpReg);

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