clang-format and add correct flags to the tests

Author: hiraditya

llvm/lib/Target/RISCV/RISCVLiveVariables.cpp

@@ -35,8 +35,8 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 
-#include <unordered_map>
 #include <set>
+#include <unordered_map>
 
 using namespace llvm;
 
@@ -385,8 +385,8 @@ void RISCVLiveVariables::verifyLiveness(MachineFunction &MF) const {
 }
 
 void RISCVLiveVariables::markKills(MachineFunction &MF) {
-    auto KillSetSize = PreRegAlloc ? RegCounter : TRI->getNumRegs();
-    for (MachineBasicBlock *MBB : post_order(&MF)) {
+  auto KillSetSize = PreRegAlloc ? RegCounter : TRI->getNumRegs();
+  for (MachineBasicBlock *MBB : post_order(&MF)) {
     // Set all the registers that are not live-out of the block.
     // Since the global liveness is available (even though a bit conservative),
     // this initialization is safe.
@@ -405,7 +405,8 @@ void RISCVLiveVariables::markKills(MachineFunction &MF) {
 
         Register Reg = MO.getReg();
         // Does not track physical registers pre-regalloc.
-        if ((PreRegAlloc && Reg.isPhysical()) || !isTrackableRegister(Reg, TRI, MRI))
+        if ((PreRegAlloc && Reg.isPhysical()) ||
+            !isTrackableRegister(Reg, TRI, MRI))
           continue;
 
         assert(TrackedRegisters.find(Reg) != TrackedRegisters.end() &&

llvm/test/CodeGen/RISCV/live-variables-basic.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=riscv-live-variables -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=riscv64 -riscv-enable-live-variables -verify-machineinstrs -o - %s | FileCheck %s
 #
 # Test basic live variable analysis with simple control flow and basic blocks
 

llvm/test/CodeGen/RISCV/live-variables-calls.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=riscv-live-variables -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=riscv64 -riscv-enable-live-variables -verify-machineinstrs -o - %s | FileCheck %s
 #
 # Test live variable analysis with function calls and register clobbering
 # Function calls clobber caller-saved registers, which affects liveness

llvm/test/CodeGen/RISCV/live-variables-edge-cases.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=riscv-live-variables -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=riscv64 -riscv-enable-live-variables -verify-machineinstrs -o - %s | FileCheck %s
 #
 # Test live variable analysis edge cases and special scenarios
 # Including: dead code, unreachable blocks, critical edges, and complex phi nodes

llvm/test/CodeGen/RISCV/live-variables-loops.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=riscv-live-variables -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=riscv64 -riscv-enable-live-variables -verify-machineinstrs -o - %s | FileCheck %s
 #
 # Test live variable analysis with loops and backward edges
 # Loops create interesting liveness patterns with phi nodes and variables

llvm/test/CodeGen/RISCV/live-variables-rv64.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=riscv-live-variables -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=riscv64 -riscv-enable-live-variables -verify-machineinstrs -o - %s | FileCheck %s
 #
 # Test live variable analysis for RV64-specific scenarios
 # This includes 64-bit operations, wide registers, and RV64-specific instructions
@@ -70,10 +70,9 @@ body:             |
 
     %0:gpr = COPY $x10
     %1:gpr = COPY $x11
-    ; SLLI for 64-bit shift (RV64-specific immediate range)
     %2:gpr = SLLI %0, 32
     %3:gpr = OR %2, %1
-    $x10 = COPY %3
+    %4:gpr = COPY %3
     PseudoRET implicit $x10
 ...
 ---

llvm/test/CodeGen/RISCV/machine-live-variables.mir

@@ -1,4 +1,4 @@
-# RUN: llc -x mir -mtriple=riscv64 -verify-machineinstrs -run-pass=riscv-live-variables -debug < %s 2>&1 \
+# RUN: llc -x mir -mtriple=riscv64 -verify-machineinstrs -riscv-enable-live-variables -debug < %s 2>&1 \
 # RUN: | FileCheck %s
 
 # REQUIRES: asserts