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Enable indiviual crbits tracking at O2
1 parent dfa665f commit d10bfa5

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5 files changed

+53
-51
lines changed

5 files changed

+53
-51
lines changed

‎clang/lib/Basic/Targets/PPC.cpp‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -559,11 +559,6 @@ bool PPCTargetInfo::initFeatureMap(
559559
.Case("pwr9", true)
560560
.Case("pwr8", true)
561561
.Default(false);
562-
Features["crbits"] = llvm::StringSwitch<bool>(CPU)
563-
.Case("ppc64le", true)
564-
.Case("pwr9", true)
565-
.Case("pwr8", true)
566-
.Default(false);
567562
Features["vsx"] = llvm::StringSwitch<bool>(CPU)
568563
.Case("ppc64le", true)
569564
.Case("pwr9", true)

‎llvm/lib/Target/PowerPC/PPC.td‎

Lines changed: 43 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
7474

7575
// Specify if we should store and manipulate i1 values in the individual
7676
// condition register bits.
77-
def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
77+
def FeatureCRBits : SubtargetFeature<"crbits", "HasCRBits", "true",
7878
"Use condition-register bits individually">;
7979
def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true",
8080
"Enable classic FPU instructions",
@@ -390,6 +390,7 @@ def ProcessorFeatures {
390390
FeatureFPCVT,
391391
FeatureISEL,
392392
FeaturePOPCNTD,
393+
FeatureCRBits,
393394
FeatureCMPB,
394395
FeatureLDBRX,
395396
Feature64Bit,
@@ -577,79 +578,82 @@ include "GISel/PPCRegisterBanks.td"
577578
//
578579

579580
def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
580-
FeatureMFTB]>;
581+
FeatureMFTB, FeatureCRBits]>;
581582
def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
582583
FeatureFRES, FeatureFRSQRTE,
583584
FeatureICBT, FeatureBookE,
584-
FeatureMSYNC, FeatureMFTB]>;
585+
FeatureMSYNC, FeatureMFTB,
586+
FeatureCRBits]>;
585587
def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
586588
FeatureFRES, FeatureFRSQRTE,
587589
FeatureICBT, FeatureBookE,
588-
FeatureMSYNC, FeatureMFTB]>;
589-
def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
590+
FeatureMSYNC, FeatureMFTB,
591+
FeatureCRBits]>;
592+
def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU,
593+
FeatureCRBits]>;
590594
def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
591-
FeatureMFTB]>;
592-
def : Processor<"603", G3Itineraries, [Directive603,
593-
FeatureFRES, FeatureFRSQRTE,
594-
FeatureMFTB]>;
595-
def : Processor<"603e", G3Itineraries, [Directive603,
596-
FeatureFRES, FeatureFRSQRTE,
597-
FeatureMFTB]>;
595+
FeatureMFTB, FeatureCRBits]>;
596+
def : Processor<"603", G3Itineraries, [Directive603, FeatureFRES,
597+
FeatureFRSQRTE, FeatureMFTB,
598+
FeatureCRBits]>;
599+
def : Processor<"603e", G3Itineraries, [Directive603, FeatureFRES,
600+
FeatureFRSQRTE, FeatureMFTB,
601+
FeatureCRBits]>;
598602
def : Processor<"603ev", G3Itineraries, [Directive603,
599603
FeatureFRES, FeatureFRSQRTE,
600-
FeatureMFTB]>;
604+
FeatureMFTB, FeatureCRBits]>;
601605
def : Processor<"604", G3Itineraries, [Directive604,
602606
FeatureFRES, FeatureFRSQRTE,
603-
FeatureMFTB]>;
607+
FeatureMFTB, FeatureCRBits]>;
604608
def : Processor<"604e", G3Itineraries, [Directive604,
605609
FeatureFRES, FeatureFRSQRTE,
606-
FeatureMFTB]>;
610+
FeatureMFTB, FeatureCRBits]>;
607611
def : Processor<"620", G3Itineraries, [Directive620,
608612
FeatureFRES, FeatureFRSQRTE,
609-
FeatureMFTB]>;
613+
FeatureMFTB, FeatureCRBits]>;
610614
def : Processor<"750", G4Itineraries, [Directive750,
611615
FeatureFRES, FeatureFRSQRTE,
612-
FeatureMFTB]>;
616+
FeatureMFTB, FeatureCRBits]>;
613617
def : Processor<"g3", G3Itineraries, [Directive750,
614618
FeatureFRES, FeatureFRSQRTE,
615-
FeatureMFTB]>;
619+
FeatureMFTB, FeatureCRBits]>;
616620
def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
617621
FeatureFRES, FeatureFRSQRTE,
618-
FeatureMFTB]>;
622+
FeatureMFTB, FeatureCRBits]>;
619623
def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
620624
FeatureFRES, FeatureFRSQRTE,
621-
FeatureMFTB]>;
625+
FeatureMFTB, FeatureCRBits]>;
622626
def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
623627
FeatureFRES, FeatureFRSQRTE,
624-
FeatureMFTB]>;
628+
FeatureMFTB, FeatureCRBits]>;
625629
def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
626630
FeatureFRES, FeatureFRSQRTE,
627-
FeatureMFTB]>;
631+
FeatureMFTB, FeatureCRBits]>;
628632

629633
def : ProcessorModel<"970", G5Model,
630634
[Directive970, FeatureAltivec,
631635
FeatureMFOCRF, FeatureFSqrt,
632636
FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
633637
Feature64Bit /*, Feature64BitRegs */,
634-
FeatureMFTB]>;
638+
FeatureMFTB, FeatureCRBits]>;
635639
def : ProcessorModel<"g5", G5Model,
636640
[Directive970, FeatureAltivec,
637641
FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
638642
FeatureFRES, FeatureFRSQRTE,
639643
Feature64Bit /*, Feature64BitRegs */,
640-
FeatureMFTB, DeprecatedDST]>;
644+
FeatureMFTB, DeprecatedDST, FeatureCRBits]>;
641645
def : ProcessorModel<"e500", PPCE500Model,
642-
[DirectiveE500,
643-
FeatureICBT, FeatureBookE,
644-
FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
646+
[DirectiveE500, FeatureICBT, FeatureBookE,
647+
FeatureISEL, FeatureMFTB, FeatureMSYNC,
648+
FeatureSPE, FeatureCRBits]>;
645649
def : ProcessorModel<"e500mc", PPCE500mcModel,
646650
[DirectiveE500mc,
647651
FeatureSTFIWX, FeatureICBT, FeatureBookE,
648-
FeatureISEL, FeatureMFTB]>;
652+
FeatureISEL, FeatureMFTB, FeatureCRBits]>;
649653
def : ProcessorModel<"e5500", PPCE5500Model,
650654
[DirectiveE5500, FeatureMFOCRF, Feature64Bit,
651655
FeatureSTFIWX, FeatureICBT, FeatureBookE,
652-
FeatureISEL, FeatureMFTB]>;
656+
FeatureISEL, FeatureMFTB, FeatureCRBits]>;
653657
def : ProcessorModel<"a2", PPCA2Model,
654658
[DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
655659
FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
@@ -658,41 +662,41 @@ def : ProcessorModel<"a2", PPCA2Model,
658662
FeatureFPRND, FeatureFPCVT, FeatureISEL,
659663
FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
660664
Feature64Bit /*, Feature64BitRegs */, FeatureMFTB,
661-
FeatureISA2_06]>;
665+
FeatureISA2_06, FeatureCRBits]>;
662666
def : ProcessorModel<"pwr3", G5Model,
663667
[DirectivePwr3, FeatureAltivec,
664668
FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
665-
FeatureSTFIWX, Feature64Bit]>;
669+
FeatureSTFIWX, Feature64Bit, FeatureCRBits]>;
666670
def : ProcessorModel<"pwr4", G5Model,
667671
[DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
668672
FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
669-
FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
673+
FeatureSTFIWX, Feature64Bit, FeatureMFTB, FeatureCRBits]>;
670674
def : ProcessorModel<"pwr5", G5Model,
671675
[DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
672676
FeatureFSqrt, FeatureFRE, FeatureFRES,
673677
FeatureFRSQRTE, FeatureFRSQRTES,
674678
FeatureSTFIWX, Feature64Bit,
675-
FeatureMFTB, DeprecatedDST]>;
679+
FeatureMFTB, DeprecatedDST, FeatureCRBits]>;
676680
def : ProcessorModel<"pwr5x", G5Model,
677681
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
678682
FeatureFSqrt, FeatureFRE, FeatureFRES,
679683
FeatureFRSQRTE, FeatureFRSQRTES,
680684
FeatureSTFIWX, FeatureFPRND, Feature64Bit,
681-
FeatureMFTB, DeprecatedDST]>;
685+
FeatureMFTB, DeprecatedDST, FeatureCRBits]>;
682686
def : ProcessorModel<"pwr6", G5Model,
683687
[DirectivePwr6, FeatureAltivec,
684688
FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
685689
FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
686690
FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
687691
FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
688-
FeatureMFTB, DeprecatedDST]>;
692+
FeatureMFTB, DeprecatedDST, FeatureCRBits]>;
689693
def : ProcessorModel<"pwr6x", G5Model,
690694
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
691695
FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
692696
FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
693697
FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
694698
FeatureFPRND, Feature64Bit,
695-
FeatureMFTB, DeprecatedDST]>;
699+
FeatureMFTB, DeprecatedDST, FeatureCRBits]>;
696700
def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
697701
def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
698702
def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
@@ -702,15 +706,15 @@ def : ProcessorModel<"pwr11", P10Model, ProcessorFeatures.P11Features>;
702706
def : ProcessorModel<"future", NoSchedModel,
703707
ProcessorFeatures.FutureFeatures>;
704708
def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
705-
FeatureMFTB]>;
709+
FeatureMFTB, FeatureCRBits]>;
706710
def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
707-
FeatureMFTB]>;
711+
FeatureMFTB, FeatureCRBits]>;
708712
def : ProcessorModel<"ppc64", G5Model,
709713
[Directive64, FeatureAltivec,
710714
FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
711715
FeatureFRSQRTE, FeatureSTFIWX,
712716
Feature64Bit /*, Feature64BitRegs */,
713-
FeatureMFTB]>;
717+
FeatureMFTB, FeatureCRBits]>;
714718
def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
715719

716720
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/PowerPC/PPCSubtarget.cpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626
#include "llvm/IR/GlobalValue.h"
2727
#include "llvm/IR/GlobalVariable.h"
2828
#include "llvm/MC/TargetRegistry.h"
29+
#include "llvm/Support/CodeGen.h"
2930
#include "llvm/Support/CommandLine.h"
3031
#include "llvm/Target/TargetMachine.h"
3132
#include "llvm/TargetParser/PPCTargetParser.h"
@@ -149,6 +150,14 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
149150
false);
150151
}
151152

153+
bool PPCSubtarget::useCRBits() const {
154+
if (!hasCRBits())
155+
return false;
156+
if (CPUDirective >= PPC::DIR_PWR8)
157+
return true;
158+
return TM.getOptLevel() >= CodeGenOptLevel::Default;
159+
}
160+
152161
bool PPCSubtarget::enableMachineScheduler() const { return true; }
153162

154163
bool PPCSubtarget::enableMachinePipeliner() const {

‎llvm/lib/Target/PowerPC/PPCSubtarget.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -209,6 +209,7 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
209209
}
210210

211211
POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
212+
bool useCRBits() const;
212213

213214
const Triple &getTargetTriple() const { return TargetTriple; }
214215

‎llvm/lib/Target/PowerPC/PPCTargetMachine.cpp‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -210,13 +210,6 @@ static std::string computeFSAdditions(StringRef FS, CodeGenOptLevel OL,
210210
FullFS = "+64bit";
211211
}
212212

213-
if (OL >= CodeGenOptLevel::Default) {
214-
if (!FullFS.empty())
215-
FullFS = "+crbits," + FullFS;
216-
else
217-
FullFS = "+crbits";
218-
}
219-
220213
if (OL != CodeGenOptLevel::None) {
221214
if (!FullFS.empty())
222215
FullFS = "+invariant-function-descriptors," + FullFS;

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