[RISCV] Add scheduling model for XiangShan-KunMingHu

The "XiangShan" is a high-performance open-source RISC-V processor project, and The "KunMingHu" architecture is its third generation. Official documentation can be found at:[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/).

This Pull Request introduces the foundational scheduling model of the KunMingHu architecture. It encompasses the basic configurations and instruction latencies of the KunMingHu core. Other components will be submitted in subsequent patches.

Co-authored-by:
Chen Jian<[email protected]>
Lv Fang<[email protected]>

Co-Authored-By: Khao7342 <[email protected]>
Co-Authored-By: huxuan0307 <[email protected]>
Co-Authored-By: Ziyue-Zhang <[email protected]>
Co-Authored-By: Lin Wang <[email protected]>
Co-Authored-By: ict-ql <[email protected]>
Co-Authored-By: bdne159 <[email protected]>
Co-Authored-By: Zhuke-bosc <[email protected]>
Co-Authored-By: 雷电霸王龙 <[email protected]>

Author: 9 people

llvm/lib/Target/RISCV/RISCV.td

@@ -52,6 +52,7 @@ include "RISCVSchedSiFiveP400.td"
 include "RISCVSchedSiFiveP600.td"
 include "RISCVSchedSyntacoreSCR1.td"
 include "RISCVSchedXiangShanNanHu.td"
+include "RISCVSchedXiangShanKunMingHu.td"
 
 //===----------------------------------------------------------------------===//
 // RISC-V processors supported.

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -380,7 +380,7 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneShiftedZExtWFusion]>;
 
 def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
-                                              NoSchedModel,
+                                              XiangShanKunMingHuModel,
                                               [Feature64Bit,
                                                FeatureStdExtI,
                                                FeatureStdExtZicsr,