Skip to content

Commit d116c37

Browse files
lquinn2015lquinn2015
committed
[RISCV] XQCIA 0.4. The spec was recently updated, this changes the name in the TD files associated and increments the Extension number in the clang driver. This is mostly a MC change as there is no other generated code for these instructions yet.
Signed-off-by: Luke Quinn <[email protected]>
1 parent 11766a4 commit d116c37

File tree

8 files changed

+32
-32
lines changed

8 files changed

+32
-32
lines changed

‎clang/test/Driver/print-supported-extensions-riscv.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -193,7 +193,7 @@
193193
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
194194
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
195195
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
196-
// CHECK-NEXT: xqcia 0.2 'Xqcia' (Qualcomm uC Arithmetic Extension)
196+
// CHECK-NEXT: xqcia 0.4 'Xqcia' (Qualcomm uC Arithmetic Extension)
197197
// CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)
198198
// CHECK-NEXT: xqcicli 0.2 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)
199199
// CHECK-NEXT: xqcicm 0.2 'Xqcicm' (Qualcomm uC Conditional Move Extension)

‎llvm/docs/RISCVUsage.rst‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -430,7 +430,7 @@ The current vendor extensions supported are:
430430
LLVM implements `the custom compressed opcodes present in some QingKe cores` by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes by the name "XW".
431431

432432
``experimental-Xqcia``
433-
LLVM implements `version 0.2 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
433+
LLVM implements `version 0.4 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
434434

435435
``experimental-Xqciac``
436436
LLVM implements `version 0.3 of the Qualcomm uC Load-Store Address Calculation extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1305,7 +1305,7 @@ def HasVendorXqcisls
13051305
"'Xqcisls' (Qualcomm uC Scaled Load Store Extension)">;
13061306

13071307
def FeatureVendorXqcia
1308-
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Arithmetic Extension">;
1308+
: RISCVExperimentalExtension<0, 4, "Qualcomm uC Arithmetic Extension">;
13091309
def HasVendorXqcia
13101310
: Predicate<"Subtarget->hasVendorXqcia()">,
13111311
AssemblerPredicate<(all_of FeatureVendorXqcia),

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -309,8 +309,8 @@ let Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" in {
309309

310310
let Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" in {
311311
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
312-
def QC_SLASAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.slasat">;
313-
def QC_SLLSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.sllsat">;
312+
def QC_SHLSAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.shlsat">;
313+
def QC_SHLUSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.shlusat">;
314314
def QC_ADDSAT : QCIRVInstRR<0b01110, GPRNoX0, "qc.addsat">;
315315
def QC_ADDUSAT : QCIRVInstRR<0b01111, GPRNoX0, "qc.addusat">;
316316
def QC_SUBSAT : QCIRVInstRR<0b10000, GPRNoX0, "qc.subsat">;

‎llvm/test/CodeGen/RISCV/attributes.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -398,7 +398,7 @@
398398
; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
399399
; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
400400
; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2"
401-
; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p2"
401+
; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p4"
402402
; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p3"
403403
; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p2"
404404
; RV32XQCICM: .attribute 5, "rv32i2p1_zca1p0_xqcicm0p2"

‎llvm/test/MC/RISCV/xqcia-invalid.s‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -6,48 +6,48 @@
66

77
# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0)
88
# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
9-
qc.slasat x10, x3, 17
9+
qc.shlsat x10, x3, 17
1010

1111
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
12-
qc.slasat x10, x3
12+
qc.shlsat x10, x3
1313

1414
# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0)
1515
# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
16-
qc.slasat x0, x3, x17
16+
qc.shlsat x0, x3, x17
1717

1818
# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
1919
# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
20-
qc.slasat x10, x0, x17
20+
qc.shlsat x10, x0, x17
2121

2222
# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0)
2323
# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
24-
qc.slasat x10, x3, x0
24+
qc.shlsat x10, x3, x0
2525

2626
# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
27-
qc.slasat x10, x3, x17
27+
qc.shlsat x10, x3, x17
2828

2929

30-
# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)
31-
# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
32-
qc.sllsat x23, x25, 27
30+
# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero (x0)
31+
# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction
32+
qc.shlusat x23, x25, 27
3333

3434
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
35-
qc.sllsat x23, x25
35+
qc.shlusat x23, x25
3636

37-
# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0)
38-
# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
39-
qc.sllsat x0, x25, x27
37+
# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
38+
# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
39+
qc.shlusat x0, x25, x27
4040

41-
# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
42-
# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
43-
qc.sllsat x23, x0, x27
41+
# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding zero (x0)
42+
# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction
43+
qc.shlusat x23, x0, x27
4444

45-
# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)
46-
# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
47-
qc.sllsat x23, x25, x0
45+
# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero (x0)
46+
# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction
47+
qc.shlusat x23, x25, x0
4848

4949
# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
50-
qc.sllsat x23, x25, x27
50+
qc.shlusat x23, x25, x27
5151

5252

5353
# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)

‎llvm/test/MC/RISCV/xqcia-valid.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,13 +10,13 @@
1010
# RUN: | llvm-objdump --mattr=+experimental-xqcia --no-print-imm-hex -d - \
1111
# RUN: | FileCheck -check-prefix=CHECK-INST %s
1212

13-
# CHECK-INST: qc.slasat a0, gp, a7
13+
# CHECK-INST: qc.shlsat a0, gp, a7
1414
# CHECK-ENC: encoding: [0x0b,0xb5,0x11,0x15]
15-
qc.slasat x10, x3, x17
15+
qc.shlsat x10, x3, x17
1616

17-
# CHECK-INST: qc.sllsat s7, s9, s11
17+
# CHECK-INST: qc.shlusat s7, s9, s11
1818
# CHECK-ENC: encoding: [0x8b,0xbb,0xbc,0x19]
19-
qc.sllsat x23, x25, x27
19+
qc.shlusat x23, x25, x27
2020

2121
# CHECK-INST: qc.addsat a7, a4, t2
2222
# CHECK-ENC: encoding: [0x8b,0x38,0x77,0x1c]

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -654,7 +654,7 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
654654
}
655655

656656
for (StringRef Input :
657-
{"rv64i_xqcisls0p2", "rv64i_xqcia0p2", "rv64i_xqciac0p3",
657+
{"rv64i_xqcisls0p2", "rv64i_xqcia0p4", "rv64i_xqciac0p3",
658658
"rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcicm0p2",
659659
"rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p2",
660660
"rv64i_xqcilo0p2", "rv64i_xqcilia0p2"}) {
@@ -1119,7 +1119,7 @@ Experimental extensions
11191119
smctr 1.0
11201120
ssctr 1.0
11211121
svukte 0.3
1122-
xqcia 0.2
1122+
xqcia 0.4
11231123
xqciac 0.3
11241124
xqcicli 0.2
11251125
xqcicm 0.2

0 commit comments

Comments
 (0)