Skip to content

Commit d11c912

Browse files
davemgreendavemgreen
committed
[AArch64][GlobalISel] Addition GISel testing for u/s add_sat and sub_sat. NFC
1 parent 0a888fa commit d11c912

File tree

12 files changed

+1022
-404
lines changed

12 files changed

+1022
-404
lines changed

‎llvm/test/CodeGen/AArch64/sadd_sat.ll‎

Lines changed: 106 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
2+
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4+
5+
; CHECK-GI: warning: Instruction selection used fallback path for vec
36

47
declare i4 @llvm.sadd.sat.i4(i4, i4)
58
declare i8 @llvm.sadd.sat.i8(i8, i8)
@@ -9,74 +12,128 @@ declare i64 @llvm.sadd.sat.i64(i64, i64)
912
declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
1013

1114
define i32 @func(i32 %x, i32 %y) nounwind {
12-
; CHECK-LABEL: func:
13-
; CHECK: // %bb.0:
14-
; CHECK-NEXT: adds w8, w0, w1
15-
; CHECK-NEXT: asr w9, w8, #31
16-
; CHECK-NEXT: eor w9, w9, #0x80000000
17-
; CHECK-NEXT: csel w0, w9, w8, vs
18-
; CHECK-NEXT: ret
15+
; CHECK-SD-LABEL: func:
16+
; CHECK-SD: // %bb.0:
17+
; CHECK-SD-NEXT: adds w8, w0, w1
18+
; CHECK-SD-NEXT: asr w9, w8, #31
19+
; CHECK-SD-NEXT: eor w9, w9, #0x80000000
20+
; CHECK-SD-NEXT: csel w0, w9, w8, vs
21+
; CHECK-SD-NEXT: ret
22+
;
23+
; CHECK-GI-LABEL: func:
24+
; CHECK-GI: // %bb.0:
25+
; CHECK-GI-NEXT: mov w8, #-2147483648 // =0x80000000
26+
; CHECK-GI-NEXT: adds w9, w0, w1
27+
; CHECK-GI-NEXT: cset w10, vs
28+
; CHECK-GI-NEXT: add w8, w8, w9, asr #31
29+
; CHECK-GI-NEXT: tst w10, #0x1
30+
; CHECK-GI-NEXT: csel w0, w8, w9, ne
31+
; CHECK-GI-NEXT: ret
1932
%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
2033
ret i32 %tmp;
2134
}
2235

2336
define i64 @func2(i64 %x, i64 %y) nounwind {
24-
; CHECK-LABEL: func2:
25-
; CHECK: // %bb.0:
26-
; CHECK-NEXT: adds x8, x0, x1
27-
; CHECK-NEXT: asr x9, x8, #63
28-
; CHECK-NEXT: eor x9, x9, #0x8000000000000000
29-
; CHECK-NEXT: csel x0, x9, x8, vs
30-
; CHECK-NEXT: ret
37+
; CHECK-SD-LABEL: func2:
38+
; CHECK-SD: // %bb.0:
39+
; CHECK-SD-NEXT: adds x8, x0, x1
40+
; CHECK-SD-NEXT: asr x9, x8, #63
41+
; CHECK-SD-NEXT: eor x9, x9, #0x8000000000000000
42+
; CHECK-SD-NEXT: csel x0, x9, x8, vs
43+
; CHECK-SD-NEXT: ret
44+
;
45+
; CHECK-GI-LABEL: func2:
46+
; CHECK-GI: // %bb.0:
47+
; CHECK-GI-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
48+
; CHECK-GI-NEXT: adds x9, x0, x1
49+
; CHECK-GI-NEXT: cset w10, vs
50+
; CHECK-GI-NEXT: add x8, x8, x9, asr #63
51+
; CHECK-GI-NEXT: tst w10, #0x1
52+
; CHECK-GI-NEXT: csel x0, x8, x9, ne
53+
; CHECK-GI-NEXT: ret
3154
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
3255
ret i64 %tmp;
3356
}
3457

3558
define i16 @func16(i16 %x, i16 %y) nounwind {
36-
; CHECK-LABEL: func16:
37-
; CHECK: // %bb.0:
38-
; CHECK-NEXT: sxth w8, w0
39-
; CHECK-NEXT: mov w9, #32767 // =0x7fff
40-
; CHECK-NEXT: add w8, w8, w1, sxth
41-
; CHECK-NEXT: cmp w8, w9
42-
; CHECK-NEXT: csel w8, w8, w9, lt
43-
; CHECK-NEXT: mov w9, #-32768 // =0xffff8000
44-
; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
45-
; CHECK-NEXT: csel w0, w8, w9, gt
46-
; CHECK-NEXT: ret
59+
; CHECK-SD-LABEL: func16:
60+
; CHECK-SD: // %bb.0:
61+
; CHECK-SD-NEXT: sxth w8, w0
62+
; CHECK-SD-NEXT: mov w9, #32767 // =0x7fff
63+
; CHECK-SD-NEXT: add w8, w8, w1, sxth
64+
; CHECK-SD-NEXT: cmp w8, w9
65+
; CHECK-SD-NEXT: csel w8, w8, w9, lt
66+
; CHECK-SD-NEXT: mov w9, #-32768 // =0xffff8000
67+
; CHECK-SD-NEXT: cmn w8, #8, lsl #12 // =32768
68+
; CHECK-SD-NEXT: csel w0, w8, w9, gt
69+
; CHECK-SD-NEXT: ret
70+
;
71+
; CHECK-GI-LABEL: func16:
72+
; CHECK-GI: // %bb.0:
73+
; CHECK-GI-NEXT: sxth w8, w1
74+
; CHECK-GI-NEXT: add w8, w8, w0, sxth
75+
; CHECK-GI-NEXT: sxth w9, w8
76+
; CHECK-GI-NEXT: asr w10, w9, #15
77+
; CHECK-GI-NEXT: cmp w8, w9
78+
; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
79+
; CHECK-GI-NEXT: csel w0, w10, w8, ne
80+
; CHECK-GI-NEXT: ret
4781
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);
4882
ret i16 %tmp;
4983
}
5084

5185
define i8 @func8(i8 %x, i8 %y) nounwind {
52-
; CHECK-LABEL: func8:
53-
; CHECK: // %bb.0:
54-
; CHECK-NEXT: sxtb w9, w0
55-
; CHECK-NEXT: mov w8, #127 // =0x7f
56-
; CHECK-NEXT: add w9, w9, w1, sxtb
57-
; CHECK-NEXT: cmp w9, #127
58-
; CHECK-NEXT: csel w8, w9, w8, lt
59-
; CHECK-NEXT: mov w9, #-128 // =0xffffff80
60-
; CHECK-NEXT: cmn w8, #128
61-
; CHECK-NEXT: csel w0, w8, w9, gt
62-
; CHECK-NEXT: ret
86+
; CHECK-SD-LABEL: func8:
87+
; CHECK-SD: // %bb.0:
88+
; CHECK-SD-NEXT: sxtb w9, w0
89+
; CHECK-SD-NEXT: mov w8, #127 // =0x7f
90+
; CHECK-SD-NEXT: add w9, w9, w1, sxtb
91+
; CHECK-SD-NEXT: cmp w9, #127
92+
; CHECK-SD-NEXT: csel w8, w9, w8, lt
93+
; CHECK-SD-NEXT: mov w9, #-128 // =0xffffff80
94+
; CHECK-SD-NEXT: cmn w8, #128
95+
; CHECK-SD-NEXT: csel w0, w8, w9, gt
96+
; CHECK-SD-NEXT: ret
97+
;
98+
; CHECK-GI-LABEL: func8:
99+
; CHECK-GI: // %bb.0:
100+
; CHECK-GI-NEXT: sxtb w8, w1
101+
; CHECK-GI-NEXT: add w8, w8, w0, sxtb
102+
; CHECK-GI-NEXT: sxtb w9, w8
103+
; CHECK-GI-NEXT: asr w10, w9, #7
104+
; CHECK-GI-NEXT: cmp w8, w9
105+
; CHECK-GI-NEXT: sub w10, w10, #128
106+
; CHECK-GI-NEXT: csel w0, w10, w8, ne
107+
; CHECK-GI-NEXT: ret
63108
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);
64109
ret i8 %tmp;
65110
}
66111

67112
define i4 @func3(i4 %x, i4 %y) nounwind {
68-
; CHECK-LABEL: func3:
69-
; CHECK: // %bb.0:
70-
; CHECK-NEXT: lsl w9, w1, #28
71-
; CHECK-NEXT: sbfx w10, w0, #0, #4
72-
; CHECK-NEXT: mov w8, #7 // =0x7
73-
; CHECK-NEXT: add w9, w10, w9, asr #28
74-
; CHECK-NEXT: cmp w9, #7
75-
; CHECK-NEXT: csel w8, w9, w8, lt
76-
; CHECK-NEXT: mov w9, #-8 // =0xfffffff8
77-
; CHECK-NEXT: cmn w8, #8
78-
; CHECK-NEXT: csel w0, w8, w9, gt
79-
; CHECK-NEXT: ret
113+
; CHECK-SD-LABEL: func3:
114+
; CHECK-SD: // %bb.0:
115+
; CHECK-SD-NEXT: lsl w9, w1, #28
116+
; CHECK-SD-NEXT: sbfx w10, w0, #0, #4
117+
; CHECK-SD-NEXT: mov w8, #7 // =0x7
118+
; CHECK-SD-NEXT: add w9, w10, w9, asr #28
119+
; CHECK-SD-NEXT: cmp w9, #7
120+
; CHECK-SD-NEXT: csel w8, w9, w8, lt
121+
; CHECK-SD-NEXT: mov w9, #-8 // =0xfffffff8
122+
; CHECK-SD-NEXT: cmn w8, #8
123+
; CHECK-SD-NEXT: csel w0, w8, w9, gt
124+
; CHECK-SD-NEXT: ret
125+
;
126+
; CHECK-GI-LABEL: func3:
127+
; CHECK-GI: // %bb.0:
128+
; CHECK-GI-NEXT: sbfx w8, w0, #0, #4
129+
; CHECK-GI-NEXT: sbfx w9, w1, #0, #4
130+
; CHECK-GI-NEXT: add w8, w8, w9
131+
; CHECK-GI-NEXT: sbfx w9, w8, #0, #4
132+
; CHECK-GI-NEXT: asr w10, w9, #3
133+
; CHECK-GI-NEXT: cmp w8, w9
134+
; CHECK-GI-NEXT: add w10, w10, #8
135+
; CHECK-GI-NEXT: csel w0, w10, w8, ne
136+
; CHECK-GI-NEXT: ret
80137
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
81138
ret i4 %tmp;
82139
}

‎llvm/test/CodeGen/AArch64/sadd_sat_plus.ll‎

Lines changed: 114 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
2+
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
34

45
declare i4 @llvm.sadd.sat.i4(i4, i4)
56
declare i8 @llvm.sadd.sat.i8(i8, i8)
@@ -8,83 +9,143 @@ declare i32 @llvm.sadd.sat.i32(i32, i32)
89
declare i64 @llvm.sadd.sat.i64(i64, i64)
910

1011
define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
11-
; CHECK-LABEL: func32:
12-
; CHECK: // %bb.0:
13-
; CHECK-NEXT: mul w8, w1, w2
14-
; CHECK-NEXT: adds w8, w0, w8
15-
; CHECK-NEXT: asr w9, w8, #31
16-
; CHECK-NEXT: eor w9, w9, #0x80000000
17-
; CHECK-NEXT: csel w0, w9, w8, vs
18-
; CHECK-NEXT: ret
12+
; CHECK-SD-LABEL: func32:
13+
; CHECK-SD: // %bb.0:
14+
; CHECK-SD-NEXT: mul w8, w1, w2
15+
; CHECK-SD-NEXT: adds w8, w0, w8
16+
; CHECK-SD-NEXT: asr w9, w8, #31
17+
; CHECK-SD-NEXT: eor w9, w9, #0x80000000
18+
; CHECK-SD-NEXT: csel w0, w9, w8, vs
19+
; CHECK-SD-NEXT: ret
20+
;
21+
; CHECK-GI-LABEL: func32:
22+
; CHECK-GI: // %bb.0:
23+
; CHECK-GI-NEXT: mul w8, w1, w2
24+
; CHECK-GI-NEXT: mov w9, #-2147483648 // =0x80000000
25+
; CHECK-GI-NEXT: adds w8, w0, w8
26+
; CHECK-GI-NEXT: cset w10, vs
27+
; CHECK-GI-NEXT: add w9, w9, w8, asr #31
28+
; CHECK-GI-NEXT: tst w10, #0x1
29+
; CHECK-GI-NEXT: csel w0, w9, w8, ne
30+
; CHECK-GI-NEXT: ret
1931
%a = mul i32 %y, %z
2032
%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
2133
ret i32 %tmp
2234
}
2335

2436
define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
25-
; CHECK-LABEL: func64:
26-
; CHECK: // %bb.0:
27-
; CHECK-NEXT: adds x8, x0, x2
28-
; CHECK-NEXT: asr x9, x8, #63
29-
; CHECK-NEXT: eor x9, x9, #0x8000000000000000
30-
; CHECK-NEXT: csel x0, x9, x8, vs
31-
; CHECK-NEXT: ret
37+
; CHECK-SD-LABEL: func64:
38+
; CHECK-SD: // %bb.0:
39+
; CHECK-SD-NEXT: adds x8, x0, x2
40+
; CHECK-SD-NEXT: asr x9, x8, #63
41+
; CHECK-SD-NEXT: eor x9, x9, #0x8000000000000000
42+
; CHECK-SD-NEXT: csel x0, x9, x8, vs
43+
; CHECK-SD-NEXT: ret
44+
;
45+
; CHECK-GI-LABEL: func64:
46+
; CHECK-GI: // %bb.0:
47+
; CHECK-GI-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
48+
; CHECK-GI-NEXT: adds x9, x0, x2
49+
; CHECK-GI-NEXT: cset w10, vs
50+
; CHECK-GI-NEXT: add x8, x8, x9, asr #63
51+
; CHECK-GI-NEXT: tst w10, #0x1
52+
; CHECK-GI-NEXT: csel x0, x8, x9, ne
53+
; CHECK-GI-NEXT: ret
3254
%a = mul i64 %y, %z
3355
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
3456
ret i64 %tmp
3557
}
3658

3759
define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
38-
; CHECK-LABEL: func16:
39-
; CHECK: // %bb.0:
40-
; CHECK-NEXT: mul w8, w1, w2
41-
; CHECK-NEXT: sxth w9, w0
42-
; CHECK-NEXT: add w8, w9, w8, sxth
43-
; CHECK-NEXT: mov w9, #32767 // =0x7fff
44-
; CHECK-NEXT: cmp w8, w9
45-
; CHECK-NEXT: csel w8, w8, w9, lt
46-
; CHECK-NEXT: mov w9, #-32768 // =0xffff8000
47-
; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
48-
; CHECK-NEXT: csel w0, w8, w9, gt
49-
; CHECK-NEXT: ret
60+
; CHECK-SD-LABEL: func16:
61+
; CHECK-SD: // %bb.0:
62+
; CHECK-SD-NEXT: mul w8, w1, w2
63+
; CHECK-SD-NEXT: sxth w9, w0
64+
; CHECK-SD-NEXT: add w8, w9, w8, sxth
65+
; CHECK-SD-NEXT: mov w9, #32767 // =0x7fff
66+
; CHECK-SD-NEXT: cmp w8, w9
67+
; CHECK-SD-NEXT: csel w8, w8, w9, lt
68+
; CHECK-SD-NEXT: mov w9, #-32768 // =0xffff8000
69+
; CHECK-SD-NEXT: cmn w8, #8, lsl #12 // =32768
70+
; CHECK-SD-NEXT: csel w0, w8, w9, gt
71+
; CHECK-SD-NEXT: ret
72+
;
73+
; CHECK-GI-LABEL: func16:
74+
; CHECK-GI: // %bb.0:
75+
; CHECK-GI-NEXT: mul w8, w1, w2
76+
; CHECK-GI-NEXT: sxth w8, w8
77+
; CHECK-GI-NEXT: add w8, w8, w0, sxth
78+
; CHECK-GI-NEXT: sxth w9, w8
79+
; CHECK-GI-NEXT: asr w10, w9, #15
80+
; CHECK-GI-NEXT: cmp w8, w9
81+
; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
82+
; CHECK-GI-NEXT: csel w0, w10, w8, ne
83+
; CHECK-GI-NEXT: ret
5084
%a = mul i16 %y, %z
5185
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
5286
ret i16 %tmp
5387
}
5488

5589
define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
56-
; CHECK-LABEL: func8:
57-
; CHECK: // %bb.0:
58-
; CHECK-NEXT: mul w8, w1, w2
59-
; CHECK-NEXT: sxtb w9, w0
60-
; CHECK-NEXT: add w8, w9, w8, sxtb
61-
; CHECK-NEXT: mov w9, #127 // =0x7f
62-
; CHECK-NEXT: cmp w8, #127
63-
; CHECK-NEXT: csel w8, w8, w9, lt
64-
; CHECK-NEXT: mov w9, #-128 // =0xffffff80
65-
; CHECK-NEXT: cmn w8, #128
66-
; CHECK-NEXT: csel w0, w8, w9, gt
67-
; CHECK-NEXT: ret
90+
; CHECK-SD-LABEL: func8:
91+
; CHECK-SD: // %bb.0:
92+
; CHECK-SD-NEXT: mul w8, w1, w2
93+
; CHECK-SD-NEXT: sxtb w9, w0
94+
; CHECK-SD-NEXT: add w8, w9, w8, sxtb
95+
; CHECK-SD-NEXT: mov w9, #127 // =0x7f
96+
; CHECK-SD-NEXT: cmp w8, #127
97+
; CHECK-SD-NEXT: csel w8, w8, w9, lt
98+
; CHECK-SD-NEXT: mov w9, #-128 // =0xffffff80
99+
; CHECK-SD-NEXT: cmn w8, #128
100+
; CHECK-SD-NEXT: csel w0, w8, w9, gt
101+
; CHECK-SD-NEXT: ret
102+
;
103+
; CHECK-GI-LABEL: func8:
104+
; CHECK-GI: // %bb.0:
105+
; CHECK-GI-NEXT: mul w8, w1, w2
106+
; CHECK-GI-NEXT: sxtb w8, w8
107+
; CHECK-GI-NEXT: add w8, w8, w0, sxtb
108+
; CHECK-GI-NEXT: sxtb w9, w8
109+
; CHECK-GI-NEXT: asr w10, w9, #7
110+
; CHECK-GI-NEXT: cmp w8, w9
111+
; CHECK-GI-NEXT: sub w10, w10, #128
112+
; CHECK-GI-NEXT: csel w0, w10, w8, ne
113+
; CHECK-GI-NEXT: ret
68114
%a = mul i8 %y, %z
69115
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
70116
ret i8 %tmp
71117
}
72118

73119
define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
74-
; CHECK-LABEL: func4:
75-
; CHECK: // %bb.0:
76-
; CHECK-NEXT: mul w8, w1, w2
77-
; CHECK-NEXT: sbfx w9, w0, #0, #4
78-
; CHECK-NEXT: lsl w8, w8, #28
79-
; CHECK-NEXT: add w8, w9, w8, asr #28
80-
; CHECK-NEXT: mov w9, #7 // =0x7
81-
; CHECK-NEXT: cmp w8, #7
82-
; CHECK-NEXT: csel w8, w8, w9, lt
83-
; CHECK-NEXT: mov w9, #-8 // =0xfffffff8
84-
; CHECK-NEXT: cmn w8, #8
85-
; CHECK-NEXT: csel w0, w8, w9, gt
86-
; CHECK-NEXT: ret
120+
; CHECK-SD-LABEL: func4:
121+
; CHECK-SD: // %bb.0:
122+
; CHECK-SD-NEXT: mul w8, w1, w2
123+
; CHECK-SD-NEXT: sbfx w9, w0, #0, #4
124+
; CHECK-SD-NEXT: lsl w8, w8, #28
125+
; CHECK-SD-NEXT: add w8, w9, w8, asr #28
126+
; CHECK-SD-NEXT: mov w9, #7 // =0x7
127+
; CHECK-SD-NEXT: cmp w8, #7
128+
; CHECK-SD-NEXT: csel w8, w8, w9, lt
129+
; CHECK-SD-NEXT: mov w9, #-8 // =0xfffffff8
130+
; CHECK-SD-NEXT: cmn w8, #8
131+
; CHECK-SD-NEXT: csel w0, w8, w9, gt
132+
; CHECK-SD-NEXT: ret
133+
;
134+
; CHECK-GI-LABEL: func4:
135+
; CHECK-GI: // %bb.0:
136+
; CHECK-GI-NEXT: mul w8, w1, w2
137+
; CHECK-GI-NEXT: sbfx w9, w0, #0, #4
138+
; CHECK-GI-NEXT: sbfx w8, w8, #0, #4
139+
; CHECK-GI-NEXT: add w8, w9, w8
140+
; CHECK-GI-NEXT: sbfx w9, w8, #0, #4
141+
; CHECK-GI-NEXT: asr w10, w9, #3
142+
; CHECK-GI-NEXT: cmp w8, w9
143+
; CHECK-GI-NEXT: add w10, w10, #8
144+
; CHECK-GI-NEXT: csel w0, w10, w8, ne
145+
; CHECK-GI-NEXT: ret
87146
%a = mul i4 %y, %z
88147
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)
89148
ret i4 %tmp
90149
}
150+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
151+
; CHECK: {{.*}}

0 commit comments

Comments
 (0)