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abhishek-kaushik22abhishek-kaushik22
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[X86][AVX512] Add pseudos for AVX512_*_SETALLONES (#169009)
Introduce `AVX512_128_SETALLONES`, `AVX512_256_SETALLONES` pseudos to generate all-ones vectors. Post-RA expansion: - Use VEX vpcmpeqd for XMM/YMM0–15 when available (matches current codegen as `AVX512_128/256_SETALLONES` will be preferred over `AVX1/2_SETALLONES` for AVX512VL target). - Use EVEX `vpternlogd imm=0xFF` for high regs. Includes MIR tests for both VEX and EVEX paths.
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‎llvm/lib/Target/X86/X86InstrAVX512.td‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -300,6 +300,12 @@ def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
300300
[(set VR512:$dst, (v16i32 immAllZerosV))]>;
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def AVX512_512_SETALLONES : I<0, Pseudo, (outs VR512:$dst), (ins), "",
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[(set VR512:$dst, (v16i32 immAllOnesV))]>;
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let AddedComplexity = 1, Predicates = [HasVLX] in {
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def AVX512_128_SETALLONES : I<0, Pseudo, (outs VR128X:$dst), (ins),
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"", [(set VR128X:$dst, (v4i32 immAllOnesV))]>;
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def AVX512_256_SETALLONES : I<0, Pseudo, (outs VR256X:$dst), (ins),
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"", [(set VR256X:$dst, (v8i32 immAllOnesV))]>;
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}
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}
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let Predicates = [HasAVX512] in {

‎llvm/lib/Target/X86/X86InstrInfo.cpp‎

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -778,6 +778,8 @@ bool X86InstrInfo::isReMaterializableImpl(
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case X86::AVX512_128_SET0:
779779
case X86::AVX512_256_SET0:
780780
case X86::AVX512_512_SET0:
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case X86::AVX512_128_SETALLONES:
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case X86::AVX512_256_SETALLONES:
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case X86::AVX512_512_SETALLONES:
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case X86::AVX512_FsFLD0SD:
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case X86::AVX512_FsFLD0SH:
@@ -6246,9 +6248,31 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
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return true;
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}
6251+
case X86::AVX512_128_SETALLONES:
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case X86::AVX512_256_SETALLONES:
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case X86::AVX512_512_SETALLONES: {
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Register Reg = MIB.getReg(0);
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MIB->setDesc(get(X86::VPTERNLOGDZrri));
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unsigned Opc;
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switch (MI.getOpcode()) {
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case X86::AVX512_128_SETALLONES: {
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if (X86::VR128RegClass.contains(Reg))
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return Expand2AddrUndef(MIB, get(X86::VPCMPEQDrr));
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Opc = X86::VPTERNLOGDZ128rri;
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break;
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}
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case X86::AVX512_256_SETALLONES: {
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if (X86::VR256RegClass.contains(Reg))
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return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
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Opc = X86::VPTERNLOGDZ256rri;
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break;
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}
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case X86::AVX512_512_SETALLONES:
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Opc = X86::VPTERNLOGDZrri;
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break;
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}
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MIB->setDesc(get(Opc));
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// VPTERNLOGD needs 3 register inputs and an immediate.
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// 0xff will return 1s for any input.
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MIB.addReg(Reg, RegState::Undef)
@@ -8190,13 +8214,15 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
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case X86::AVX1_SETALLONES:
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case X86::AVX_SET0:
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case X86::AVX512_256_SET0:
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case X86::AVX512_256_SETALLONES:
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Alignment = Align(32);
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break;
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case X86::V_SET0:
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case X86::V_SETALLONES:
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case X86::AVX512_128_SET0:
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case X86::FsFLD0F128:
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case X86::AVX512_FsFLD0F128:
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case X86::AVX512_128_SETALLONES:
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Alignment = Align(16);
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break;
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case X86::MMX_SET0:
@@ -8255,6 +8281,8 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
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case X86::AVX512_128_SET0:
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case X86::AVX512_256_SET0:
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case X86::AVX512_512_SET0:
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case X86::AVX512_128_SETALLONES:
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case X86::AVX512_256_SETALLONES:
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case X86::AVX512_512_SETALLONES:
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case X86::FsFLD0SH:
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case X86::AVX512_FsFLD0SH:
@@ -8315,6 +8343,7 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
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break;
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case X86::AVX1_SETALLONES:
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case X86::AVX2_SETALLONES:
8346+
case X86::AVX512_256_SETALLONES:
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IsAllOnes = true;
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[[fallthrough]];
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case X86::AVX512_256_SET0:
@@ -8328,6 +8357,7 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
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2);
83298358
break;
83308359
case X86::V_SETALLONES:
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case X86::AVX512_128_SETALLONES:
83318361
IsAllOnes = true;
83328362
[[fallthrough]];
83338363
case X86::V_SET0:

‎llvm/test/CodeGen/X86/avx512-i386-setallones-pseudo.mir‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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# RUN: llc %s -mtriple=i386-- -start-before=postrapseudos -o - | FileCheck %s
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--- |
5+
target triple = "i386-unknown-unknown"
6+
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define void @setallones() #0 {
8+
; CHECK-LABEL: setallones:
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; CHECK: # %bb.0:
10+
; CHECK-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
11+
; CHECK-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
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entry:
13+
unreachable
14+
}
15+
16+
attributes #0 = { "target-features"="+avx512f,+avx512vl" }
17+
---
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name: setallones
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tracksRegLiveness: true
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liveins: []
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body: |
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bb.0:
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$xmm0 = AVX512_128_SETALLONES
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$ymm1 = AVX512_256_SETALLONES
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...

‎llvm/test/CodeGen/X86/avx512-setallones-pseudo.mir‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
# RUN: llc %s -mtriple=x86_64-- -start-before=postrapseudos -o - | FileCheck %s
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--- |
5+
target triple = "x86_64-unknown-unknown"
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7+
define void @setallones() #0 {
8+
; CHECK-LABEL: setallones:
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; CHECK: # %bb.0:
10+
; CHECK-NEXT: vpcmpeqd %xmm14, %xmm14, %xmm14
11+
; CHECK-NEXT: vpternlogd {{.*#+}} xmm16 = -1
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; CHECK-NEXT: vpcmpeqd %ymm15, %ymm15, %ymm15
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; CHECK-NEXT: vpternlogd {{.*#+}} ymm17 = -1
14+
entry:
15+
unreachable
16+
}
17+
18+
attributes #0 = { "target-features"="+avx512f,+avx512vl" }
19+
---
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name: setallones
21+
tracksRegLiveness: true
22+
liveins: []
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body: |
24+
bb.0:
25+
$xmm14 = AVX512_128_SETALLONES
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$xmm16 = AVX512_128_SETALLONES
27+
$ymm15 = AVX512_256_SETALLONES
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$ymm17 = AVX512_256_SETALLONES
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...

‎llvm/test/CodeGen/X86/eq-or-eq-range-of-2.ll‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,8 @@ define <4 x i32> @eq_or_eq_ult_2_fail_multiuse(<4 x i32> %x) {
106106
; AVX512: # %bb.0:
107107
; AVX512-NEXT: subq $24, %rsp
108108
; AVX512-NEXT: .cfi_def_cfa_offset 32
109-
; AVX512-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
109+
; AVX512-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
110+
; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
110111
; AVX512-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
111112
; AVX512-NEXT: callq use.v4.i32@PLT
112113
; AVX512-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload

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