[Xtensa] Minor fixed in disassembler and subtarget. Fix boolean test.

Author: andreisfr

llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp

@@ -57,7 +57,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaDisassembler() {
                                          createXtensaDisassembler);
 }
 
-const unsigned ARDecoderTable[] = {
+const MCPhysReg ARDecoderTable[] = {
     Xtensa::A0,  Xtensa::SP,  Xtensa::A2,  Xtensa::A3, Xtensa::A4,  Xtensa::A5,
     Xtensa::A6,  Xtensa::A7,  Xtensa::A8,  Xtensa::A9, Xtensa::A10, Xtensa::A11,
     Xtensa::A12, Xtensa::A13, Xtensa::A14, Xtensa::A15};
@@ -68,12 +68,12 @@ static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo,
   if (RegNo >= std::size(ARDecoderTable))
     return MCDisassembler::Fail;
 
-  unsigned Reg = ARDecoderTable[RegNo];
+  MCPhysReg Reg = ARDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-const unsigned SRDecoderTable[] = {
+const MCPhysReg SRDecoderTable[] = {
     Xtensa::SAR, 3, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
 
 static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
@@ -84,7 +84,7 @@ static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
 
   for (unsigned i = 0; i < std::size(SRDecoderTable); i += 2) {
     if (SRDecoderTable[i + 1] == RegNo) {
-      unsigned Reg = SRDecoderTable[i];
+      MCPhysReg Reg = SRDecoderTable[i];
 
       if (!Xtensa::checkRegister(Reg,
                                  Decoder->getSubtargetInfo().getFeatureBits()))
@@ -98,7 +98,7 @@ static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
   return MCDisassembler::Fail;
 }
 
-const unsigned BRDecoderTable[] = {
+const MCPhysReg BRDecoderTable[] = {
     Xtensa::B0,  Xtensa::B1,  Xtensa::B2,  Xtensa::B3, Xtensa::B4,  Xtensa::B5,
     Xtensa::B6,  Xtensa::B7,  Xtensa::B8,  Xtensa::B9, Xtensa::B10, Xtensa::B11,
     Xtensa::B12, Xtensa::B13, Xtensa::B14, Xtensa::B15};
@@ -109,7 +109,7 @@ static DecodeStatus DecodeBRRegisterClass(MCInst &Inst, uint64_t RegNo,
   if (RegNo >= std::size(BRDecoderTable))
     return MCDisassembler::Fail;
 
-  unsigned Reg = BRDecoderTable[RegNo];
+  MCPhysReg Reg = BRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }

llvm/lib/Target/Xtensa/XtensaSubtarget.cpp

@@ -30,8 +30,6 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
     CPUName = "generic";
   }
 
-  HasDensity = false;
-
   // Parse features string.
   ParseSubtargetFeatures(CPUName, CPUName, FS);
   return *this;

llvm/lib/Target/Xtensa/XtensaSubtarget.h

@@ -36,14 +36,10 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
   SelectionDAGTargetInfo TSInfo;
   XtensaFrameLowering FrameLowering;
 
-  // Enabled Xtensa Density Option
-  bool HasDensity;
-
-  // Enabled Xtensa Windowed Register Option
-  bool HasWindowed;
-
-  // Enabled Boolean Option
-  bool HasBoolean;
+// Bool members corresponding to the SubtargetFeatures defined in tablegen
+#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER)                    \
+  bool ATTRIBUTE = DEFAULT;
+#include "XtensaGenSubtargetInfo.inc"
 
   XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 

llvm/test/MC/Xtensa/boolean.s

@@ -1,5 +1,5 @@
 # RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+bool \
-# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK %s
 
 .align	4
 // CHECK: .p2align	4