@@ -180,14 +180,14 @@ class ZvkMxSet<string vd_lmul> {
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!eq(vd_lmul, "MF8") : [V_MF8]);
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}
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- class VPseudoUnaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass, string Constraint = "" > :
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+ class VPseudoUnaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
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Pseudo<(outs RetClass:$rd),
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(ins RetClass:$merge, OpClass:$rs2, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
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RISCVVPseudo {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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- let Constraints = !interleave([Constraint, "$rd = $merge"], ",") ;
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+ let Constraints = "$rd = $merge";
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let HasVLOp = 1;
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let HasSEWOp = 1;
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let HasVecPolicyOp = 1;
@@ -196,16 +196,15 @@ class VPseudoUnaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass, string Constrain
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class VPseudoBinaryNoMask_Zvk<VReg RetClass,
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VReg Op1Class,
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- DAGOperand Op2Class,
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- string Constraint> :
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+ DAGOperand Op2Class> :
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Pseudo<(outs RetClass:$rd),
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(ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1,
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AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
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RISCVVPseudo {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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- let Constraints = !interleave([Constraint, "$rd = $merge"], ",") ;
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+ let Constraints = "$rd = $merge";
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let HasVLOp = 1;
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let HasSEWOp = 1;
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let HasVecPolicyOp = 1;
@@ -215,98 +214,90 @@ class VPseudoBinaryNoMask_Zvk<VReg RetClass,
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multiclass VPseudoBinaryNoMask_Zvk<VReg RetClass,
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VReg Op1Class,
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DAGOperand Op2Class,
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- LMULInfo MInfo,
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- string Constraint = ""> {
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+ LMULInfo MInfo> {
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let VLMul = MInfo.value in
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- def "_" # MInfo.MX : VPseudoBinaryNoMask_Zvk<RetClass, Op1Class, Op2Class,
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- Constraint>;
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+ def "_" # MInfo.MX : VPseudoBinaryNoMask_Zvk<RetClass, Op1Class, Op2Class>;
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}
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- multiclass VPseudoUnaryV_V_NoMask_Zvk<LMULInfo m, string Constraint = "" > {
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+ multiclass VPseudoUnaryV_V_NoMask_Zvk<LMULInfo m> {
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let VLMul = m.value in {
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- def "_VV_" # m.MX : VPseudoUnaryNoMask_Zvk<m.vrclass, m.vrclass, Constraint >;
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+ def "_VV_" # m.MX : VPseudoUnaryNoMask_Zvk<m.vrclass, m.vrclass>;
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}
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}
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- multiclass VPseudoUnaryV_S_NoMask_Zvk<LMULInfo m, string Constraint = "" > {
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+ multiclass VPseudoUnaryV_S_NoMask_Zvk<LMULInfo m> {
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let VLMul = m.value in
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foreach vs2_lmul = ZvkMxSet<m.MX>.vs2_lmuls in
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- def "_VS_" # m.MX # "_" # vs2_lmul.MX : VPseudoUnaryNoMask_Zvk<m.vrclass, vs2_lmul.vrclass, Constraint >;
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+ def "_VS_" # m.MX # "_" # vs2_lmul.MX : VPseudoUnaryNoMask_Zvk<m.vrclass, vs2_lmul.vrclass>;
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}
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- multiclass VPseudoVALU_V_NoMask_Zvk<string Constraint = ""> {
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+ multiclass VPseudoVALU_V_NoMask_Zvk {
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foreach m = MxListVF4 in {
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defvar mx = m.MX;
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defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
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defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
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- defm "" : VPseudoUnaryV_V_NoMask_Zvk<m, Constraint >,
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+ defm "" : VPseudoUnaryV_V_NoMask_Zvk<m>,
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Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
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}
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}
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- multiclass VPseudoVALU_S_NoMask_Zvk<string Constraint = ""> {
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+ multiclass VPseudoVALU_S_NoMask_Zvk {
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foreach m = MxListVF4 in {
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defvar mx = m.MX;
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defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
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defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
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- defm "" : VPseudoUnaryV_S_NoMask_Zvk<m, Constraint >,
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+ defm "" : VPseudoUnaryV_S_NoMask_Zvk<m>,
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Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
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}
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}
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- multiclass VPseudoVALU_V_S_NoMask_Zvk<string Constraint = ""> {
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- defm "" : VPseudoVALU_V_NoMask_Zvk<Constraint> ;
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- defm "" : VPseudoVALU_S_NoMask_Zvk<Constraint> ;
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+ multiclass VPseudoVALU_V_S_NoMask_Zvk {
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+ defm "" : VPseudoVALU_V_NoMask_Zvk;
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+ defm "" : VPseudoVALU_S_NoMask_Zvk;
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}
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- multiclass VPseudoVALU_VV_NoMask_Zvk<string Constraint = ""> {
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+ multiclass VPseudoVALU_VV_NoMask_Zvk {
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foreach m = MxListVF4 in {
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defvar mx = m.MX;
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defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
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defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
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- defm _VV : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m,
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- Constraint>,
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+ defm _VV : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m>,
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Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
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}
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}
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- multiclass VPseudoVALU_VI_NoMask_Zvk<Operand ImmType = simm5,
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- string Constraint = ""> {
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+ multiclass VPseudoVALU_VI_NoMask_Zvk<Operand ImmType = simm5> {
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foreach m = MxListVF4 in {
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defvar mx = m.MX;
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defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
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defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
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- defm _VI : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass, ImmType, m,
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- Constraint>,
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+ defm _VI : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass, ImmType, m>,
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Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
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}
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}
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- multiclass VPseudoVALU_VI_NoMaskTU_Zvk<Operand ImmType = uimm5,
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- string Constraint = ""> {
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+ multiclass VPseudoVALU_VI_NoMaskTU_Zvk<Operand ImmType = uimm5> {
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foreach m = MxListVF4 in {
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defvar mx = m.MX;
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defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
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defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
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- defm _VI : VPseudoBinaryNoMask<m.vrclass, m.vrclass, ImmType, m,
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- Constraint>,
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+ defm _VI : VPseudoBinaryNoMask<m.vrclass, m.vrclass, ImmType, m>,
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Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
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}
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}
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- multiclass VPseudoVALU_VV_NoMaskTU_Zvk<string Constraint = ""> {
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+ multiclass VPseudoVALU_VV_NoMaskTU_Zvk {
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foreach m = MxListVF4 in {
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defvar mx = m.MX;
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defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
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defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
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- defm _VV : VPseudoBinaryNoMask<m.vrclass, m.vrclass, m.vrclass, m,
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- Constraint>,
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+ defm _VV : VPseudoBinaryNoMask<m.vrclass, m.vrclass, m.vrclass, m>,
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Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
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}
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}
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