Skip to content

Commit d19d8e0

Browse files
committed
[RISCV] Remove unused Constraint template parameter from RISCVInstrInfoZvk.td. NFC
1 parent 487720f commit d19d8e0

File tree

1 file changed

+25
-34
lines changed

1 file changed

+25
-34
lines changed

llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Lines changed: 25 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -180,14 +180,14 @@ class ZvkMxSet<string vd_lmul> {
180180
!eq(vd_lmul, "MF8") : [V_MF8]);
181181
}
182182

183-
class VPseudoUnaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass, string Constraint = ""> :
183+
class VPseudoUnaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
184184
Pseudo<(outs RetClass:$rd),
185185
(ins RetClass:$merge, OpClass:$rs2, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
186186
RISCVVPseudo {
187187
let mayLoad = 0;
188188
let mayStore = 0;
189189
let hasSideEffects = 0;
190-
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
190+
let Constraints = "$rd = $merge";
191191
let HasVLOp = 1;
192192
let HasSEWOp = 1;
193193
let HasVecPolicyOp = 1;
@@ -196,16 +196,15 @@ class VPseudoUnaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass, string Constrain
196196

197197
class VPseudoBinaryNoMask_Zvk<VReg RetClass,
198198
VReg Op1Class,
199-
DAGOperand Op2Class,
200-
string Constraint> :
199+
DAGOperand Op2Class> :
201200
Pseudo<(outs RetClass:$rd),
202201
(ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1,
203202
AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
204203
RISCVVPseudo {
205204
let mayLoad = 0;
206205
let mayStore = 0;
207206
let hasSideEffects = 0;
208-
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
207+
let Constraints = "$rd = $merge";
209208
let HasVLOp = 1;
210209
let HasSEWOp = 1;
211210
let HasVecPolicyOp = 1;
@@ -215,98 +214,90 @@ class VPseudoBinaryNoMask_Zvk<VReg RetClass,
215214
multiclass VPseudoBinaryNoMask_Zvk<VReg RetClass,
216215
VReg Op1Class,
217216
DAGOperand Op2Class,
218-
LMULInfo MInfo,
219-
string Constraint = ""> {
217+
LMULInfo MInfo> {
220218
let VLMul = MInfo.value in
221-
def "_" # MInfo.MX : VPseudoBinaryNoMask_Zvk<RetClass, Op1Class, Op2Class,
222-
Constraint>;
219+
def "_" # MInfo.MX : VPseudoBinaryNoMask_Zvk<RetClass, Op1Class, Op2Class>;
223220
}
224221

225-
multiclass VPseudoUnaryV_V_NoMask_Zvk<LMULInfo m, string Constraint = ""> {
222+
multiclass VPseudoUnaryV_V_NoMask_Zvk<LMULInfo m> {
226223
let VLMul = m.value in {
227-
def "_VV_" # m.MX : VPseudoUnaryNoMask_Zvk<m.vrclass, m.vrclass, Constraint>;
224+
def "_VV_" # m.MX : VPseudoUnaryNoMask_Zvk<m.vrclass, m.vrclass>;
228225
}
229226
}
230227

231-
multiclass VPseudoUnaryV_S_NoMask_Zvk<LMULInfo m, string Constraint = ""> {
228+
multiclass VPseudoUnaryV_S_NoMask_Zvk<LMULInfo m> {
232229
let VLMul = m.value in
233230
foreach vs2_lmul = ZvkMxSet<m.MX>.vs2_lmuls in
234-
def "_VS_" # m.MX # "_" # vs2_lmul.MX : VPseudoUnaryNoMask_Zvk<m.vrclass, vs2_lmul.vrclass, Constraint>;
231+
def "_VS_" # m.MX # "_" # vs2_lmul.MX : VPseudoUnaryNoMask_Zvk<m.vrclass, vs2_lmul.vrclass>;
235232
}
236233

237-
multiclass VPseudoVALU_V_NoMask_Zvk<string Constraint = ""> {
234+
multiclass VPseudoVALU_V_NoMask_Zvk {
238235
foreach m = MxListVF4 in {
239236
defvar mx = m.MX;
240237
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
241238
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
242239

243-
defm "" : VPseudoUnaryV_V_NoMask_Zvk<m, Constraint>,
240+
defm "" : VPseudoUnaryV_V_NoMask_Zvk<m>,
244241
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
245242
}
246243
}
247244

248-
multiclass VPseudoVALU_S_NoMask_Zvk<string Constraint = ""> {
245+
multiclass VPseudoVALU_S_NoMask_Zvk {
249246
foreach m = MxListVF4 in {
250247
defvar mx = m.MX;
251248
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
252249
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
253250

254-
defm "" : VPseudoUnaryV_S_NoMask_Zvk<m, Constraint>,
251+
defm "" : VPseudoUnaryV_S_NoMask_Zvk<m>,
255252
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
256253
}
257254
}
258255

259-
multiclass VPseudoVALU_V_S_NoMask_Zvk<string Constraint = ""> {
260-
defm "" : VPseudoVALU_V_NoMask_Zvk<Constraint>;
261-
defm "" : VPseudoVALU_S_NoMask_Zvk<Constraint>;
256+
multiclass VPseudoVALU_V_S_NoMask_Zvk {
257+
defm "" : VPseudoVALU_V_NoMask_Zvk;
258+
defm "" : VPseudoVALU_S_NoMask_Zvk;
262259
}
263260

264-
multiclass VPseudoVALU_VV_NoMask_Zvk<string Constraint = ""> {
261+
multiclass VPseudoVALU_VV_NoMask_Zvk {
265262
foreach m = MxListVF4 in {
266263
defvar mx = m.MX;
267264
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
268265
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
269266

270-
defm _VV : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m,
271-
Constraint>,
267+
defm _VV : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m>,
272268
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
273269
}
274270
}
275271

276-
multiclass VPseudoVALU_VI_NoMask_Zvk<Operand ImmType = simm5,
277-
string Constraint = ""> {
272+
multiclass VPseudoVALU_VI_NoMask_Zvk<Operand ImmType = simm5> {
278273
foreach m = MxListVF4 in {
279274
defvar mx = m.MX;
280275
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
281276
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
282277

283-
defm _VI : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass, ImmType, m,
284-
Constraint>,
278+
defm _VI : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass, ImmType, m>,
285279
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
286280
}
287281
}
288282

289-
multiclass VPseudoVALU_VI_NoMaskTU_Zvk<Operand ImmType = uimm5,
290-
string Constraint = ""> {
283+
multiclass VPseudoVALU_VI_NoMaskTU_Zvk<Operand ImmType = uimm5> {
291284
foreach m = MxListVF4 in {
292285
defvar mx = m.MX;
293286
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
294287
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
295288

296-
defm _VI : VPseudoBinaryNoMask<m.vrclass, m.vrclass, ImmType, m,
297-
Constraint>,
289+
defm _VI : VPseudoBinaryNoMask<m.vrclass, m.vrclass, ImmType, m>,
298290
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
299291
}
300292
}
301293

302-
multiclass VPseudoVALU_VV_NoMaskTU_Zvk<string Constraint = ""> {
294+
multiclass VPseudoVALU_VV_NoMaskTU_Zvk {
303295
foreach m = MxListVF4 in {
304296
defvar mx = m.MX;
305297
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
306298
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
307299

308-
defm _VV : VPseudoBinaryNoMask<m.vrclass, m.vrclass, m.vrclass, m,
309-
Constraint>,
300+
defm _VV : VPseudoBinaryNoMask<m.vrclass, m.vrclass, m.vrclass, m>,
310301
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
311302
}
312303
}

0 commit comments

Comments
 (0)