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1 parent 5a47a18 commit d1b6ce5Copy full SHA for d1b6ce5
llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -1566,8 +1566,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
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bool hasSetPrioIncWgInst() const { return HasSetPrioIncWgInst; }
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// \returns true if S_GETPC_B64 zero-extends the result from 48 bits instead
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- // of sign-extending.
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- bool hasGetPCZeroExtension() const { return GFX12Insts; }
+ // of sign-extending. Note that GFX1250 has not only fixed the bug but also
+ // extended VA to 57 bits.
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+ bool hasGetPCZeroExtension() const { return GFX12Insts && !GFX1250Insts; }
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/// \returns SGPR allocation granularity supported by the subtarget.
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unsigned getSGPRAllocGranule() const {
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