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1 parent 95c94cb commit d1bad99Copy full SHA for d1bad99
llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -287,8 +287,8 @@ class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
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class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
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: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd),
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- (ins (CVrr $rs2, $rs1):$cvrr),
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- opcodestr, "$rd, $cvrr">;
+ (ins (CVrr $rs2, $rs1):$addr),
+ opcodestr, "$rd, $addr">;
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} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
@@ -317,8 +317,8 @@ class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, string opcodestr>
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class CVStore_rr<bits<3> funct3, bits<7> funct7, string opcodestr>
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- : RVInst<(outs), (ins GPR:$rs2, (CVrr $rs3, $rs1):$cvrr), opcodestr,
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- "$rs2, $cvrr", [], InstFormatOther> {
+ : RVInst<(outs), (ins GPR:$rs2, (CVrr $rs3, $rs1):$addr), opcodestr,
+ "$rs2, $addr", [], InstFormatOther> {
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bits<5> rs1;
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bits<5> rs2;
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bits<5> rs3;
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