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[SelectionDAG] Add DoNotPoisonEltMask to SimplifyMultipleUseDemandedBitsForTargetNode
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4 files changed

+19
-11
lines changed

4 files changed

+19
-11
lines changed

llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4388,6 +4388,7 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
43884388
/// bitwise ops etc.
43894389
virtual SDValue SimplifyMultipleUseDemandedBitsForTargetNode(
43904390
SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
4391+
const APInt &DoNotPoisonEltMask,
43914392
SelectionDAG &DAG, unsigned Depth) const;
43924393

43934394
/// Return true if this function can prove that \p Op is never poison

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1000,7 +1000,7 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
10001000

10011001
if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
10021002
if (SDValue V = SimplifyMultipleUseDemandedBitsForTargetNode(
1003-
Op, DemandedBits, DemandedElts | DoNotPoisonEltMask, DAG, Depth))
1003+
Op, DemandedBits, DemandedElts, DoNotPoisonEltMask, DAG, Depth))
10041004
return V;
10051005
break;
10061006
}
@@ -4058,12 +4058,14 @@ bool TargetLowering::SimplifyDemandedBitsForTargetNode(
40584058
Op.getOpcode() == ISD::INTRINSIC_VOID) &&
40594059
"Should use SimplifyDemandedBits if you don't know whether Op"
40604060
" is a target node!");
4061-
computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth);
4061+
computeKnownBitsForTargetNode(Op, Known, DemandedElts,
4062+
TLO.DAG, Depth);
40624063
return false;
40634064
}
40644065

40654066
SDValue TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
40664067
SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
4068+
const APInt &DoNotPoisonEltMask,
40674069
SelectionDAG &DAG, unsigned Depth) const {
40684070
assert(
40694071
(Op.getOpcode() >= ISD::BUILTIN_OP_END ||

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -43672,9 +43672,9 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
4367243672
return true;
4367343673

4367443674
if (!DemandedElts.isAllOnes()) {
43675-
SDValue NewLHS = SimplifyMultipleUseDemandedBits(LHS, BitsLHS, EltsLHS | DoNotPoisonEltMask,
43675+
SDValue NewLHS = SimplifyMultipleUseDemandedBits(LHS, BitsLHS, EltsLHS, DoNotPoisonEltMask,
4367643676
TLO.DAG, Depth + 1);
43677-
SDValue NewRHS = SimplifyMultipleUseDemandedBits(RHS, BitsRHS, EltsRHS | DoNotPoisonEltMask,
43677+
SDValue NewRHS = SimplifyMultipleUseDemandedBits(RHS, BitsRHS, EltsRHS, DoNotPoisonEltMask,
4367843678
TLO.DAG, Depth + 1);
4367943679
if (NewLHS || NewRHS) {
4368043680
NewLHS = NewLHS ? NewLHS : LHS;
@@ -43796,6 +43796,7 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
4379643796
case X86ISD::BLENDI: {
4379743797
SmallVector<int, 16> BlendMask;
4379843798
DecodeBLENDMask(NumElts, Op.getConstantOperandVal(2), BlendMask);
43799+
// TODO: Do we really need to consider the DoNotPoisonEltMask here?
4379943800
if (SDValue R = combineBlendOfPermutes(
4380043801
VT.getSimpleVT(), Op.getOperand(0), Op.getOperand(1), BlendMask,
4380143802
DemandedElts | DoNotPoisonEltMask, TLO.DAG, Subtarget, SDLoc(Op)))
@@ -44906,6 +44907,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
4490644907

4490744908
SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
4490844909
SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
44910+
const APInt &DoNotPoisonEltMask,
4490944911
SelectionDAG &DAG, unsigned Depth) const {
4491044912
int NumElts = DemandedElts.getBitWidth();
4491144913
unsigned Opc = Op.getOpcode();
@@ -44919,7 +44921,8 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
4491944921
auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4492044922
MVT VecVT = Vec.getSimpleValueType();
4492144923
if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) &&
44922-
!DemandedElts[CIdx->getZExtValue()])
44924+
!DemandedElts[CIdx->getZExtValue()] &&
44925+
!DoNotPoisonEltMask[CIdx->getZExtValue()])
4492344926
return Vec;
4492444927
break;
4492544928
}
@@ -44954,7 +44957,7 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
4495444957
SDValue LHS = Op.getOperand(1);
4495544958
SDValue RHS = Op.getOperand(2);
4495644959

44957-
KnownBits CondKnown = DAG.computeKnownBits(Cond, DemandedElts, Depth + 1);
44960+
KnownBits CondKnown = DAG.computeKnownBits(Cond, DemandedElts | DoNotPoisonEltMask, Depth + 1);
4495844961
if (CondKnown.isNegative())
4495944962
return LHS;
4496044963
if (CondKnown.isNonNegative())
@@ -44966,8 +44969,8 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
4496644969
SDValue LHS = Op.getOperand(0);
4496744970
SDValue RHS = Op.getOperand(1);
4496844971

44969-
KnownBits LHSKnown = DAG.computeKnownBits(LHS, DemandedElts, Depth + 1);
44970-
KnownBits RHSKnown = DAG.computeKnownBits(RHS, DemandedElts, Depth + 1);
44972+
KnownBits LHSKnown = DAG.computeKnownBits(LHS, DemandedElts | DoNotPoisonEltMask, Depth + 1);
44973+
KnownBits RHSKnown = DAG.computeKnownBits(RHS, DemandedElts | DoNotPoisonEltMask, Depth + 1);
4497144974

4497244975
// If all of the demanded bits are known 0 on LHS and known 0 on RHS, then
4497344976
// the (inverted) LHS bits cannot contribute to the result of the 'andn' in
@@ -44981,7 +44984,8 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
4498144984
APInt ShuffleUndef, ShuffleZero;
4498244985
SmallVector<int, 16> ShuffleMask;
4498344986
SmallVector<SDValue, 2> ShuffleOps;
44984-
if (getTargetShuffleInputs(Op, DemandedElts, ShuffleOps, ShuffleMask,
44987+
if (getTargetShuffleInputs(Op, DemandedElts | DoNotPoisonEltMask,
44988+
ShuffleOps, ShuffleMask,
4498544989
ShuffleUndef, ShuffleZero, DAG, Depth, false)) {
4498644990
// If all the demanded elts are from one operand and are inline,
4498744991
// then we can use the operand directly.
@@ -45000,7 +45004,7 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
4500045004
APInt IdentityOp = APInt::getAllOnes(NumOps);
4500145005
for (int i = 0; i != NumElts; ++i) {
4500245006
int M = ShuffleMask[i];
45003-
if (!DemandedElts[i] || ShuffleUndef[i])
45007+
if (!(DemandedElts[i] || DoNotPoisonEltMask[i]) || ShuffleUndef[i])
4500445008
continue;
4500545009
int OpIdx = M / NumElts;
4500645010
int EltIdx = M % NumElts;
@@ -45021,7 +45025,7 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
4502145025
}
4502245026

4502345027
return TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
45024-
Op, DemandedBits, DemandedElts, DAG, Depth);
45028+
Op, DemandedBits, DemandedElts, DoNotPoisonEltMask, DAG, Depth);
4502545029
}
4502645030

4502745031
bool X86TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode(

llvm/lib/Target/X86/X86ISelLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1325,6 +1325,7 @@ namespace llvm {
13251325

13261326
SDValue SimplifyMultipleUseDemandedBitsForTargetNode(
13271327
SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
1328+
const APInt &DoNotPoisonEltMask,
13281329
SelectionDAG &DAG, unsigned Depth) const override;
13291330

13301331
bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(

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