Address comments

Author: wangpc-pp

clang/lib/Basic/Targets/RISCV.cpp

@@ -395,7 +395,7 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
 
   if (ABI == "ilp32e" && ISAInfo->hasExtension("d")) {
     Diags.Report(diag::err_invalid_feature_combination)
-        << "ILP32E must not be used with the D ISA extension";
+        << "ILP32E cannot be used with the D ISA extension";
     return false;
   }
   return true;

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

@@ -294,7 +294,7 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
 
     if (MABI.equals_insensitive("ilp32e"))
       return "rv32e";
-    else if (MABI.starts_with_insensitive("lp64e"))
+    else if (MABI.equals_insensitive("lp64e"))
       return "rv64e";
     else if (MABI.starts_with_insensitive("ilp32"))
       return "rv32imafdc";

clang/test/CodeGen/RISCV/riscv32-ilp32e-error.c

@@ -1,4 +1,4 @@
 // RUN: not %clang_cc1 -triple riscv32 -target-feature +d -emit-llvm -target-abi ilp32e %s 2>&1 \
 // RUN:     | FileCheck -check-prefix=ILP32E-WITH-FD %s
 
-// ILP32E-WITH-FD: error: invalid feature combination: ILP32E must not be used with the D ISA extension
+// ILP32E-WITH-FD: error: invalid feature combination: ILP32E cannot be used with the D ISA extension

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

@@ -71,7 +71,7 @@ ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
   if ((TargetABI == RISCVABI::ABI::ABI_ILP32E ||
        (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&
       FeatureBits[RISCV::FeatureStdExtD])
-    report_fatal_error("ILP32E must not be used with the D ISA extension");
+    report_fatal_error("ILP32E cannot be used with the D ISA extension");
 
   if (TargetABI != ABI_Unknown)
     return TargetABI;

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

@@ -512,8 +512,9 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   // The following calculates the correct offset knowing the number of callee
   // saved registers spilt by the two methods.
   if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) {
-    // Calculate the size of the frame managed by the libcall. The libcalls are
-    // implemented such that the stack will always be 16 byte aligned.
+    // Calculate the size of the frame managed by the libcall. The stack
+    // alignment of these libcalls should be the same as how we set it in
+    // getABIStackAlignment.
     unsigned LibCallFrameSize =
         alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign());
     RVFI->setLibCallStackSize(LibCallFrameSize);

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -17187,10 +17187,9 @@ static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
     // Both halves must be passed on the stack, with proper alignment.
     // TODO: To be compatible with GCC's behaviors, we force them to have 4-byte
     // alignment. This behavior may be changed when RV32E/ILP32E is ratified.
-    Align StackAlign =
-        EABI && XLen == 32
-            ? Align(XLenInBytes)
-            : std::max(Align(XLenInBytes), ArgFlags1.getNonZeroOrigAlign());
+    Align StackAlign(XLenInBytes);
+    if (!EABI || XLen != 32)
+      StackAlign = std::max(StackAlign, ArgFlags1.getNonZeroOrigAlign());
     State.addLoc(
         CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(),
                             State.AllocateStack(XLenInBytes, StackAlign),

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

@@ -117,7 +117,7 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 
   // There are only 16 GPRs for RVE.
   if (STI.isRVE())
-    for (size_t Reg = RISCV::X16; Reg <= RISCV::X31; Reg++)
+    for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++)
       markSuperRegs(Reserved, Reg);
 
   // V registers for code generation. We handle them manually.

llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll

@@ -10,14 +10,7 @@
 ; RUN:   -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=ILP32E-WITHFP-SAVE-RESTORE %s
 
-; As well as calling convention details, we check that ra and fp are
-; consistently stored to fp-4 and fp-8.
-
-; Any tests that would have identical output for some combination of the ilp32*
-; ABIs belong in calling-conv-*-common.ll. This file contains tests that will
-; have different output across those ABIs. i.e. where some arguments would be
-; passed according to the floating point ABI, or where the stack is aligned to
-; a different boundary.
+; This file contains tests that will have differing output for the ilp32e ABIs.
 
 define i32 @callee_float_in_regs(i32 %a, float %b) {
 ; ILP32E-FPELIM-LABEL: callee_float_in_regs:

llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll

@@ -4,15 +4,7 @@
 ; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs -frame-pointer=all < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I-LP64E-WITHFP %s
 
-; As well as calling convention details, we check that ra and fp are
-; consistently stored to fp-8 and fp-16.
-
-; Any tests that would have identical output for some combination of the lp64*
-; ABIs belong in calling-conv-*-common.ll. This file contains tests that will
-; have different output across those ABIs. i.e. where some arguments would be
-; passed according to the floating point ABI.
-
-; TODO: softened float values can be passed anyext.
+; This file contains tests that will have differing output for the lp64e ABIs.
 
 define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
 ; RV64I-LP64E-FPELIM-LABEL: callee_float_in_regs:

llvm/test/MC/RISCV/target-abi-invalid.s

@@ -42,7 +42,7 @@
 # RV32EF-LP64F: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32EFD-LP64D: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32E-LP64E: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
-# RV32EFD-LP64D: LLVM ERROR: ILP32E must not be used with the D ISA extension
+# RV32EFD-LP64D: LLVM ERROR: ILP32E cannot be used with the D ISA extension
 
 # RUN: llvm-mc -triple=riscv32 -target-abi ilp32f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32I-ILP32F %s
@@ -78,9 +78,9 @@
 # RV32E-ILP32: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
 # RV32EF-ILP32F: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
 # RV32EFD-ILP32F: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
-# RV32EFD-ILP32F: LLVM ERROR: ILP32E must not be used with the D ISA extension
+# RV32EFD-ILP32F: LLVM ERROR: ILP32E cannot be used with the D ISA extension
 # RV32EFD-ILP32D: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
-# RV32EFD-ILP32D: LLVM ERROR: ILP32E must not be used with the D ISA extension
+# RV32EFD-ILP32D: LLVM ERROR: ILP32E cannot be used with the D ISA extension
 
 # RUN: llvm-mc -triple=riscv64 -mattr=+e -target-abi lp64 < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV64EF-LP64F %s