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‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll‎

Lines changed: 172 additions & 116 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll‎

Lines changed: 25 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22

3-
; RUN: llc -mtriple=amdgcn -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefix=GCN %s
4-
; RUN: llc -mtriple=amdgcn -mcpu=tonga -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=VI %s
5-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX9 %s
6-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX11 %s
3+
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
4+
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
5+
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
6+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
77

88
define <4 x float> @bitcast_v4i32_to_v4f32(<4 x i32> %a, i32 %b) {
99
; GCN-LABEL: bitcast_v4i32_to_v4f32:
@@ -312,9 +312,10 @@ define <4 x i32> @bitcast_v2i64_to_v4i32(<2 x i64> %a, i32 %b) {
312312
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
313313
; GFX11-NEXT: ; %bb.1: ; %cmp.true
314314
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
315-
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
315+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
316+
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
316317
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
317-
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
318+
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
318319
; GFX11-NEXT: ; %bb.2: ; %end
319320
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
320321
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2309,9 +2310,10 @@ define <4 x float> @bitcast_v2i64_to_v4f32(<2 x i64> %a, i32 %b) {
23092310
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
23102311
; GFX11-NEXT: ; %bb.1: ; %cmp.true
23112312
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
2312-
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
2313+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
2314+
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
23132315
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
2314-
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
2316+
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
23152317
; GFX11-NEXT: ; %bb.2: ; %end
23162318
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
23172319
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4215,9 +4217,10 @@ define <2 x double> @bitcast_v2i64_to_v2f64(<2 x i64> %a, i32 %b) {
42154217
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
42164218
; GFX11-NEXT: ; %bb.1: ; %cmp.true
42174219
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
4218-
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
4220+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
4221+
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
42194222
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
4220-
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
4223+
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
42214224
; GFX11-NEXT: ; %bb.2: ; %end
42224225
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
42234226
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4395,9 +4398,10 @@ define <8 x i16> @bitcast_v2i64_to_v8i16(<2 x i64> %a, i32 %b) {
43954398
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
43964399
; GFX11-NEXT: ; %bb.1: ; %cmp.true
43974400
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
4398-
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
4401+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
4402+
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
43994403
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
4400-
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
4404+
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
44014405
; GFX11-NEXT: ; %bb.2: ; %end
44024406
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
44034407
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4660,9 +4664,10 @@ define <8 x half> @bitcast_v2i64_to_v8f16(<2 x i64> %a, i32 %b) {
46604664
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
46614665
; GFX11-NEXT: ; %bb.1: ; %cmp.true
46624666
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
4663-
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
4667+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
4668+
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
46644669
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
4665-
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
4670+
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
46664671
; GFX11-NEXT: ; %bb.2: ; %end
46674672
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
46684673
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4936,9 +4941,10 @@ define <8 x bfloat> @bitcast_v2i64_to_v8bf16(<2 x i64> %a, i32 %b) {
49364941
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
49374942
; GFX11-NEXT: ; %bb.1: ; %cmp.true
49384943
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
4939-
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
4944+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
4945+
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
49404946
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
4941-
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
4947+
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
49424948
; GFX11-NEXT: ; %bb.2: ; %end
49434949
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
49444950
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5512,9 +5518,10 @@ define <16 x i8> @bitcast_v2i64_to_v16i8(<2 x i64> %a, i32 %b) {
55125518
; GFX11-NEXT: s_cbranch_execz .LBB34_4
55135519
; GFX11-NEXT: ; %bb.3: ; %cmp.true
55145520
; GFX11-NEXT: v_add_co_u32 v16, vcc_lo, v16, 3
5515-
; GFX11-NEXT: v_add_co_ci_u32_e32 v17, vcc_lo, 0, v17, vcc_lo
5521+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
5522+
; GFX11-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
55165523
; GFX11-NEXT: v_add_co_u32 v18, vcc_lo, v18, 3
5517-
; GFX11-NEXT: v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo
5524+
; GFX11-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
55185525
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
55195526
; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[16:17]
55205527
; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v17

‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22

3-
; RUN: llc -mtriple=amdgcn -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefix=GCN %s
4-
; RUN: llc -mtriple=amdgcn -mcpu=tonga -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=VI %s
5-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX9 %s
6-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX11 %s
3+
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
4+
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
5+
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
6+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
77

88
define <5 x float> @bitcast_v5i32_to_v5f32(<5 x i32> %a, i32 %b) {
99
; GCN-LABEL: bitcast_v5i32_to_v5f32:

‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22

3-
; RUN: llc -mtriple=amdgcn -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefix=GCN %s
4-
; RUN: llc -mtriple=amdgcn -mcpu=tonga -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=VI %s
5-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX9 %s
6-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX11 %s
3+
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
4+
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
5+
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
6+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
77

88
define half @bitcast_i16_to_f16(i16 %a, i32 %b) {
99
; GCN-LABEL: bitcast_i16_to_f16:

‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll‎

Lines changed: 19 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22

3-
; RUN: llc -mtriple=amdgcn -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefix=GCN %s
4-
; RUN: llc -mtriple=amdgcn -mcpu=tonga -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=VI %s
5-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX9 %s
6-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX11 %s
3+
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
4+
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
5+
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
6+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
77

88
define <6 x float> @bitcast_v6i32_to_v6f32(<6 x i32> %a, i32 %b) {
99
; GCN-LABEL: bitcast_v6i32_to_v6f32:
@@ -341,11 +341,13 @@ define <6 x i32> @bitcast_v3i64_to_v6i32(<3 x i64> %a, i32 %b) {
341341
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
342342
; GFX11-NEXT: ; %bb.1: ; %cmp.true
343343
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
344-
; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
344+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
345+
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
345346
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
346-
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
347+
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
347348
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
348-
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
349+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
350+
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
349351
; GFX11-NEXT: ; %bb.2: ; %end
350352
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
351353
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -693,11 +695,13 @@ define <6 x float> @bitcast_v3i64_to_v6f32(<3 x i64> %a, i32 %b) {
693695
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
694696
; GFX11-NEXT: ; %bb.1: ; %cmp.true
695697
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
696-
; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
698+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
699+
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
697700
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
698-
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
701+
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
699702
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
700-
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
703+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
704+
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
701705
; GFX11-NEXT: ; %bb.2: ; %end
702706
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
703707
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -954,11 +958,13 @@ define <3 x double> @bitcast_v3i64_to_v3f64(<3 x i64> %a, i32 %b) {
954958
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
955959
; GFX11-NEXT: ; %bb.1: ; %cmp.true
956960
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
957-
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
961+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
962+
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
958963
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
959-
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
964+
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
960965
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
961-
; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
966+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
967+
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
962968
; GFX11-NEXT: ; %bb.2: ; %end
963969
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
964970
; GFX11-NEXT: s_setpc_b64 s[30:31]

‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22

3-
; RUN: llc -mtriple=amdgcn -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefix=GCN %s
4-
; RUN: llc -mtriple=amdgcn -mcpu=tonga -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=VI %s
5-
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX9 %s
6-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX11 %s
3+
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
4+
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
5+
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
6+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
77

88
define <7 x float> @bitcast_v7i32_to_v7f32(<7 x i32> %a, i32 %b) {
99
; GCN-LABEL: bitcast_v7i32_to_v7f32:

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