update mod

Author: mattarde

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -219,8 +219,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
 
   // SETOEQ and SETUNE require checking two conditions.
   for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) {
-    setCondCodeAction(ISD::SETOEQ, VT, Expand);
-    setCondCodeAction(ISD::SETUNE, VT, Expand);
+    setCondCodeAction(ISD::SETOEQ, VT, Subtarget.hasAVX10_2_512() ? Custom : Expand);
+    setCondCodeAction(ISD::SETUNE, VT, Subtarget.hasAVX10_2_512() ? Custom : Expand);
   }
 
   // Integer absolute.
@@ -1056,11 +1056,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
     }
   }
 
-  if(Subtarget.hasAVX10_2_512()){
-    for (auto FVT : { MVT::f16, MVT::f32, MVT::f64 }) {
-      setOperationAction(ISD::SETCC, FVT, Custom);
-    }
-  }
   // FIXME: In order to prevent SSE instructions being expanded to MMX ones
   // with -msoft-float, disable use of MMX as well.
   if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
@@ -2447,7 +2442,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
       }
     }
   }
-
+  
   if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
     setTruncStoreAction(MVT::v4i64, MVT::v4i8,  Legal);
     setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
@@ -24078,6 +24073,14 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
     return IsStrict ? DAG.getMergeValues({Res, Chain}, dl) : Res;
   }
 
+  if(Subtarget.hasAVX10_2_512()){
+    if( CC == ISD::SETOEQ ||  CC == ISD::SETUNE){
+    auto NewCC = (CC == ISD:::SETOEQ) ? X86::COND_E : (X86::COND_NE);
+    return getSETCC(NewCC,
+                    DAG.getNode(X86ISD::UCOMX,
+                            dl, MVT::i32, Op0, Op1), dl, DAG);
+    }
+  }
   // Handle floating point.
   X86::CondCode CondCode = TranslateX86CC(CC, dl, /*IsFP*/ true, Op0, Op1, DAG);
   if (CondCode == X86::COND_INVALID)