Patch with updated test case, based on feedback.

Author: isakhilesh

llvm/test/CodeGen/AMDGPU/swdev-504645.ll renamed to llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll

@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck %s
 
 define void @test_load_zext() {
 ; CHECK-LABEL: test_load_zext:
@@ -13,8 +13,8 @@ define void @test_load_zext() {
 ; CHECK-NEXT:    s_add_i32 s32, s32, 16
 ; CHECK-NEXT:    v_writelane_b32 v40, s0, 2
 ; CHECK-NEXT:    s_getpc_b64 s[0:1]
-; CHECK-NEXT:    s_add_u32 s0, s0, test_buffer_load_sgpr_plus_imm_offset_noflags@gotpcrel32@lo+4
-; CHECK-NEXT:    s_addc_u32 s1, s1, test_buffer_load_sgpr_plus_imm_offset_noflags@gotpcrel32@hi+12
+; CHECK-NEXT:    s_add_u32 s0, s0, has_spgr_args@gotpcrel32@lo+4
+; CHECK-NEXT:    s_addc_u32 s1, s1, has_spgr_args@gotpcrel32@hi+12
 ; CHECK-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x0
 ; CHECK-NEXT:    v_writelane_b32 v40, s30, 0
 ; CHECK-NEXT:    s_mov_b32 s0, DescriptorBuffer@abs32@lo
@@ -32,14 +32,13 @@ define void @test_load_zext() {
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
 .entry:
-  %0 = call i32 @llvm.amdgcn.reloc.constant(metadata !0)
-  call void @test_buffer_load_sgpr_plus_imm_offset_noflags(i32 %0)
+  %reloc = call i32 @llvm.amdgcn.reloc.constant(metadata !0)
+  call void @has_spgr_args(i32 %reloc)
   ret void
 }
 
-declare void @test_buffer_load_sgpr_plus_imm_offset_noflags(i32 inreg)
+declare void @has_spgr_args(i32 inreg)
 
-; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
 declare i32 @llvm.amdgcn.reloc.constant(metadata) #0
 
 attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }