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sunshaocesunshaoce
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[NFC] [RISCV] Refactor class RISCVExtension (#120040)
I think typo can be avoided by reducing the number of times we re-enter the extension name.
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4 files changed

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-407
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4 files changed

+568
-407
lines changed

‎clang/test/Driver/print-enabled-extensions/riscv-rocket-rv64.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@
44
// Simple litmus test to check the frontend handling of this option is
55
// enabled.
66

7-
// CHECK: Extensions enabled for the given RISC-V target
7+
// CHECK: Extensions enabled for the given RISC-V target
88
// CHECK-EMPTY:
9-
// CHECK-NEXT: Name Version Description
10-
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
11-
// CHECK-NEXT: zicsr 2.0 'zicsr' (CSRs)
12-
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
9+
// CHECK-NEXT: Name Version Description
10+
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
11+
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
12+
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1313
// CHECK-EMPTY:

‎clang/test/Driver/print-supported-extensions-riscv.c‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
// CHECK-EMPTY:
66
// CHECK-NEXT: Name Version Description
77
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
8-
// CHECK-NEXT: e 2.0 Implements RV{32,64}E (provides 16 rather than 32 GPRs)
8+
// CHECK-NEXT: e 2.0 'E' (Embedded Instruction Set with 16 GPRs)
99
// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
1010
// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
1111
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
@@ -24,7 +24,7 @@
2424
// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)
2525
// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers)
2626
// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations)
27-
// CHECK-NEXT: zicsr 2.0 'zicsr' (CSRs)
27+
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
2828
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
2929
// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints)
3030
// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint)
@@ -78,7 +78,7 @@
7878
// CHECK-NEXT: zve64d 1.0 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)
7979
// CHECK-NEXT: zve64f 1.0 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)
8080
// CHECK-NEXT: zve64x 1.0 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)
81-
// CHECK-NEXT: zvfbfmin 1.0 'Zvbfmin' (Vector BF16 Converts)
81+
// CHECK-NEXT: zvfbfmin 1.0 'Zvfbfmin' (Vector BF16 Converts)
8282
// CHECK-NEXT: zvfbfwma 1.0 'Zvfbfwma' (Vector BF16 widening mul-add)
8383
// CHECK-NEXT: zvfh 1.0 'Zvfh' (Vector Half-Precision Floating-Point)
8484
// CHECK-NEXT: zvfhmin 1.0 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)
@@ -87,7 +87,7 @@
8787
// CHECK-NEXT: zvkn 1.0 'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt')
8888
// CHECK-NEXT: zvknc 1.0 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')
8989
// CHECK-NEXT: zvkned 1.0 'Zvkned' (Vector AES Encryption & Decryption (Single Round))
90-
// CHECK-NEXT: zvkng 1.0 'zvkng' (shorthand for 'Zvkn' and 'Zvkg')
90+
// CHECK-NEXT: zvkng 1.0 'Zvkng' (shorthand for 'Zvkn' and 'Zvkg')
9191
// CHECK-NEXT: zvknha 1.0 'Zvknha' (Vector SHA-2 (SHA-256 only))
9292
// CHECK-NEXT: zvknhb 1.0 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))
9393
// CHECK-NEXT: zvks 1.0 'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt')
@@ -96,25 +96,25 @@
9696
// CHECK-NEXT: zvksg 1.0 'Zvksg' (shorthand for 'Zvks' and 'Zvkg')
9797
// CHECK-NEXT: zvksh 1.0 'Zvksh' (SM3 Hash Function Instructions)
9898
// CHECK-NEXT: zvkt 1.0 'Zvkt' (Vector Data-Independent Execution Latency)
99-
// CHECK-NEXT: zvl1024b 1.0 'Zvl' (Minimum Vector Length) 1024
100-
// CHECK-NEXT: zvl128b 1.0 'Zvl' (Minimum Vector Length) 128
101-
// CHECK-NEXT: zvl16384b 1.0 'Zvl' (Minimum Vector Length) 16384
102-
// CHECK-NEXT: zvl2048b 1.0 'Zvl' (Minimum Vector Length) 2048
103-
// CHECK-NEXT: zvl256b 1.0 'Zvl' (Minimum Vector Length) 256
104-
// CHECK-NEXT: zvl32768b 1.0 'Zvl' (Minimum Vector Length) 32768
105-
// CHECK-NEXT: zvl32b 1.0 'Zvl' (Minimum Vector Length) 32
106-
// CHECK-NEXT: zvl4096b 1.0 'Zvl' (Minimum Vector Length) 4096
107-
// CHECK-NEXT: zvl512b 1.0 'Zvl' (Minimum Vector Length) 512
108-
// CHECK-NEXT: zvl64b 1.0 'Zvl' (Minimum Vector Length) 64
109-
// CHECK-NEXT: zvl65536b 1.0 'Zvl' (Minimum Vector Length) 65536
110-
// CHECK-NEXT: zvl8192b 1.0 'Zvl' (Minimum Vector Length) 8192
99+
// CHECK-NEXT: zvl1024b 1.0 'Zvl1024b' (Minimum Vector Length 1024)
100+
// CHECK-NEXT: zvl128b 1.0 'Zvl128b' (Minimum Vector Length 128)
101+
// CHECK-NEXT: zvl16384b 1.0 'Zvl16384b' (Minimum Vector Length 16384)
102+
// CHECK-NEXT: zvl2048b 1.0 'Zvl2048b' (Minimum Vector Length 2048)
103+
// CHECK-NEXT: zvl256b 1.0 'Zvl256b' (Minimum Vector Length 256)
104+
// CHECK-NEXT: zvl32768b 1.0 'Zvl32768b' (Minimum Vector Length 32768)
105+
// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector Length 32)
106+
// CHECK-NEXT: zvl4096b 1.0 'Zvl4096b' (Minimum Vector Length 4096)
107+
// CHECK-NEXT: zvl512b 1.0 'Zvl512b' (Minimum Vector Length 512)
108+
// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector Length 64)
109+
// CHECK-NEXT: zvl65536b 1.0 'Zvl65536b' (Minimum Vector Length 65536)
110+
// CHECK-NEXT: zvl8192b 1.0 'Zvl8192b' (Minimum Vector Length 8192)
111111
// CHECK-NEXT: zhinx 1.0 'Zhinx' (Half Float in Integer)
112112
// CHECK-NEXT: zhinxmin 1.0 'Zhinxmin' (Half Float in Integer Minimal)
113113
// CHECK-NEXT: sha 1.0 'Sha' (Augmented Hypervisor)
114114
// CHECK-NEXT: shcounterenw 1.0 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)
115-
// CHECK-NEXT: shgatpa 1.0 'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)
115+
// CHECK-NEXT: shgatpa 1.0 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)
116116
// CHECK-NEXT: shtvala 1.0 'Shtvala' (htval provides all needed values)
117-
// CHECK-NEXT: shvsatpa 1.0 'Svsatpa' (vsatp supports all modes supported by satp)
117+
// CHECK-NEXT: shvsatpa 1.0 'Shvsatpa' (vsatp supports all modes supported by satp)
118118
// CHECK-NEXT: shvstvala 1.0 'Shvstvala' (vstval provides all needed values)
119119
// CHECK-NEXT: shvstvecd 1.0 'Shvstvecd' (vstvec supports Direct mode)
120120
// CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level)
@@ -145,11 +145,11 @@
145145
// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
146146
// CHECK-NEXT: svade 1.0 'Svade' (Raise exceptions on improper A/D bits)
147147
// CHECK-NEXT: svadu 1.0 'Svadu' (Hardware A/D updates)
148-
// CHECK-NEXT: svbare 1.0 'Svbare' $(satp mode Bare supported)
148+
// CHECK-NEXT: svbare 1.0 'Svbare' (satp mode Bare supported)
149149
// CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation)
150150
// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity)
151151
// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types)
152-
// CHECK-NEXT: svvptc 1.0 'svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
152+
// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
153153
// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations)
154154
// CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching)
155155
// CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit Manipulation)

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