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[RISCV][GISel] Custom promote s32 G_FPTOSI/FPTOUI on RV64. (#115268)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to remove i32 from the GPR register class.
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12 files changed

+131
-138
lines changed

12 files changed

+131
-138
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 18 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -534,9 +534,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
534534
.legalIf(typeIsScalarFPArith(0, ST))
535535
.lowerFor({s32, s64});
536536

537-
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
538-
.legalIf(all(typeInSet(0, {s32, sXLen}), typeIsScalarFPArith(1, ST)))
539-
.widenScalarToNextPow2(0)
537+
auto &FPToIActions = getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI});
538+
FPToIActions.legalIf(all(typeInSet(0, {sXLen}), typeIsScalarFPArith(1, ST)));
539+
if (ST.is64Bit())
540+
FPToIActions.customIf(all(typeInSet(0, {s32}), typeIsScalarFPArith(1, ST)));
541+
FPToIActions.widenScalarToNextPow2(0)
540542
.minScalar(0, s32)
541543
.libcallFor({{s32, s32}, {s64, s32}, {s32, s64}, {s64, s64}})
542544
.libcallFor(ST.is64Bit(), {{s128, s32}, {s128, s64}});
@@ -1171,6 +1173,10 @@ static unsigned getRISCVWOpcode(unsigned Opcode) {
11711173
return RISCV::G_CLZW;
11721174
case TargetOpcode::G_CTTZ:
11731175
return RISCV::G_CTZW;
1176+
case TargetOpcode::G_FPTOSI:
1177+
return RISCV::G_FCVT_W_RV64;
1178+
case TargetOpcode::G_FPTOUI:
1179+
return RISCV::G_FCVT_WU_RV64;
11741180
}
11751181
}
11761182

@@ -1229,6 +1235,15 @@ bool RISCVLegalizerInfo::legalizeCustom(
12291235
Helper.Observer.changedInstr(MI);
12301236
return true;
12311237
}
1238+
case TargetOpcode::G_FPTOSI:
1239+
case TargetOpcode::G_FPTOUI: {
1240+
Helper.Observer.changingInstr(MI);
1241+
Helper.widenScalarDst(MI, sXLen);
1242+
MI.setDesc(MIRBuilder.getTII().get(getRISCVWOpcode(MI.getOpcode())));
1243+
MI.addOperand(MachineOperand::CreateImm(RISCVFPRndMode::RTZ));
1244+
Helper.Observer.changedInstr(MI);
1245+
return true;
1246+
}
12321247
case TargetOpcode::G_IS_FPCLASS: {
12331248
Register GISFPCLASS = MI.getOperand(0).getReg();
12341249
Register Src = MI.getOperand(1).getReg();

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -149,6 +149,8 @@ bool RISCVRegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
149149
const MachineRegisterInfo &MRI,
150150
const TargetRegisterInfo &TRI) const {
151151
switch (MI.getOpcode()) {
152+
case RISCV::G_FCVT_W_RV64:
153+
case RISCV::G_FCVT_WU_RV64:
152154
case TargetOpcode::G_FPTOSI:
153155
case TargetOpcode::G_FPTOUI:
154156
case TargetOpcode::G_FCMP:
@@ -432,6 +434,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
432434
OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] = Mapping;
433435
break;
434436
}
437+
case RISCV::G_FCVT_W_RV64:
438+
case RISCV::G_FCVT_WU_RV64:
435439
case TargetOpcode::G_FPTOSI:
436440
case TargetOpcode::G_FPTOUI:
437441
case RISCV::G_FCLASS: {

‎llvm/lib/Target/RISCV/RISCVInstrGISel.td‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,22 @@ def G_CTZW : RISCVGenericInstruction {
4949
}
5050
def : GINodeEquiv<G_CTZW, riscv_ctzw>;
5151

52+
// Pseudo equivalent to a RISCVISD::FCVT_W_RV64.
53+
def G_FCVT_W_RV64 : RISCVGenericInstruction {
54+
let OutOperandList = (outs type0:$dst);
55+
let InOperandList = (ins type1:$src, untyped_imm_0:$frm);
56+
let hasSideEffects = false;
57+
}
58+
def : GINodeEquiv<G_FCVT_W_RV64, riscv_fcvt_w_rv64>;
59+
60+
// Pseudo equivalent to a RISCVISD::FCVT_WU_RV64.
61+
def G_FCVT_WU_RV64 : RISCVGenericInstruction {
62+
let OutOperandList = (outs type0:$dst);
63+
let InOperandList = (ins type1:$src, untyped_imm_0:$frm);
64+
let hasSideEffects = false;
65+
}
66+
def : GINodeEquiv<G_FCVT_WU_RV64, riscv_fcvt_wu_rv64>;
67+
5268
// Pseudo equivalent to a RISCVISD::FCLASS.
5369
def G_FCLASS : RISCVGenericInstruction {
5470
let OutOperandList = (outs type0:$dst);

‎llvm/lib/Target/RISCV/RISCVInstrInfoD.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -534,7 +534,7 @@ def : Pat<(store (f64 GPRPair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$i
534534
(PseudoRV32ZdinxSD GPRPair:$rs2, GPR:$rs1, simm12:$imm12)>;
535535
} // Predicates = [HasStdExtZdinx, IsRV32]
536536

537-
let Predicates = [HasStdExtD] in {
537+
let Predicates = [HasStdExtD, IsRV32] in {
538538

539539
// double->[u]int. Round-to-zero must be used.
540540
def : Pat<(i32 (any_fp_to_sint FPR64:$rs1)), (FCVT_W_D FPR64:$rs1, FRM_RTZ)>;
@@ -553,7 +553,7 @@ def : Pat<(i32 (any_lround FPR64:$rs1)), (FCVT_W_D $rs1, FRM_RMM)>;
553553
// [u]int->double.
554554
def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1, FRM_RNE)>;
555555
def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU GPR:$rs1, FRM_RNE)>;
556-
} // Predicates = [HasStdExtD]
556+
} // Predicates = [HasStdExtD, IsRV32]
557557

558558
let Predicates = [HasStdExtZdinx, IsRV32] in {
559559

‎llvm/lib/Target/RISCV/RISCVInstrInfoF.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -720,7 +720,7 @@ def : Pat<(f32 (bitconvert (i32 GPR:$rs1))), (EXTRACT_SUBREG GPR:$rs1, sub_32)>;
720720
def : Pat<(i32 (bitconvert FPR32INX:$rs1)), (INSERT_SUBREG (XLenVT (IMPLICIT_DEF)), FPR32INX:$rs1, sub_32)>;
721721
} // Predicates = [HasStdExtZfinx]
722722

723-
let Predicates = [HasStdExtF] in {
723+
let Predicates = [HasStdExtF, IsRV32] in {
724724
// float->[u]int. Round-to-zero must be used.
725725
def : Pat<(i32 (any_fp_to_sint FPR32:$rs1)), (FCVT_W_S $rs1, FRM_RTZ)>;
726726
def : Pat<(i32 (any_fp_to_uint FPR32:$rs1)), (FCVT_WU_S $rs1, FRM_RTZ)>;
@@ -738,9 +738,9 @@ def : Pat<(i32 (any_lround FPR32:$rs1)), (FCVT_W_S $rs1, FRM_RMM)>;
738738
// [u]int->float. Match GCC and default to using dynamic rounding mode.
739739
def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W $rs1, FRM_DYN)>;
740740
def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, FRM_DYN)>;
741-
} // Predicates = [HasStdExtF]
741+
} // Predicates = [HasStdExtF, IsRV32]
742742

743-
let Predicates = [HasStdExtZfinx] in {
743+
let Predicates = [HasStdExtZfinx, IsRV32] in {
744744
// float->[u]int. Round-to-zero must be used.
745745
def : Pat<(i32 (any_fp_to_sint FPR32INX:$rs1)), (FCVT_W_S_INX $rs1, FRM_RTZ)>;
746746
def : Pat<(i32 (any_fp_to_uint FPR32INX:$rs1)), (FCVT_WU_S_INX $rs1, FRM_RTZ)>;
@@ -758,7 +758,7 @@ def : Pat<(i32 (any_lround FPR32INX:$rs1)), (FCVT_W_S_INX $rs1, FRM_RMM)>;
758758
// [u]int->float. Match GCC and default to using dynamic rounding mode.
759759
def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W_INX $rs1, FRM_DYN)>;
760760
def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU_INX $rs1, FRM_DYN)>;
761-
} // Predicates = [HasStdExtZfinx]
761+
} // Predicates = [HasStdExtZfinx, IsRV32]
762762

763763
let Predicates = [HasStdExtF, IsRV64] in {
764764
// Moves (no conversion)

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -480,7 +480,7 @@ def : Pat<(riscv_fmv_x_anyexth FPR16INX:$src), (INSERT_SUBREG (XLenVT (IMPLICIT_
480480
def : Pat<(fcopysign FPR32INX:$rs1, FPR16INX:$rs2), (FSGNJ_S_INX $rs1, (FCVT_S_H_INX $rs2, FRM_RNE))>;
481481
} // Predicates = [HasStdExtZhinxmin]
482482

483-
let Predicates = [HasStdExtZfh] in {
483+
let Predicates = [HasStdExtZfh, IsRV32] in {
484484
// half->[u]int. Round-to-zero must be used.
485485
def : Pat<(i32 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_W_H $rs1, 0b001)>;
486486
def : Pat<(i32 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_WU_H $rs1, 0b001)>;
@@ -500,7 +500,7 @@ def : Pat<(f16 (any_sint_to_fp (i32 GPR:$rs1))), (FCVT_H_W $rs1, FRM_DYN)>;
500500
def : Pat<(f16 (any_uint_to_fp (i32 GPR:$rs1))), (FCVT_H_WU $rs1, FRM_DYN)>;
501501
} // Predicates = [HasStdExtZfh]
502502

503-
let Predicates = [HasStdExtZhinx] in {
503+
let Predicates = [HasStdExtZhinx, IsRV32] in {
504504
// half->[u]int. Round-to-zero must be used.
505505
def : Pat<(i32 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, 0b001)>;
506506
def : Pat<(i32 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_WU_H_INX $rs1, 0b001)>;
@@ -518,7 +518,7 @@ def : Pat<(i32 (any_lround FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, FRM_RMM)>;
518518
// [u]int->half. Match GCC and default to using dynamic rounding mode.
519519
def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W_INX $rs1, FRM_DYN)>;
520520
def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU_INX $rs1, FRM_DYN)>;
521-
} // Predicates = [HasStdExtZhinx]
521+
} // Predicates = [HasStdExtZhinx, IsRV32]
522522

523523
let Predicates = [HasStdExtZfh, IsRV64] in {
524524
// Use target specific isd nodes to help us remember the result is sign

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -19,9 +19,8 @@ body: |
1919
; CHECK-NEXT: $x10 = COPY [[FCVT_W_H]]
2020
; CHECK-NEXT: PseudoRET implicit $x10
2121
%0:fprb(s16) = COPY $f10_h
22-
%1:gprb(s32) = G_FPTOSI %0(s16)
23-
%2:gprb(s64) = G_ANYEXT %1(s32)
24-
$x10 = COPY %2(s64)
22+
%1:gprb(s64) = G_FCVT_W_RV64 %0(s16), 1
23+
$x10 = COPY %1(s64)
2524
PseudoRET implicit $x10
2625
2726
...
@@ -42,9 +41,8 @@ body: |
4241
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_H]]
4342
; CHECK-NEXT: PseudoRET implicit $x10
4443
%0:fprb(s16) = COPY $f10_h
45-
%1:gprb(s32) = G_FPTOUI %0(s16)
46-
%2:gprb(s64) = G_ANYEXT %1(s32)
47-
$x10 = COPY %2(s64)
44+
%1:gprb(s64) = G_FCVT_WU_RV64 %0(s16), 1
45+
$x10 = COPY %1(s64)
4846
PseudoRET implicit $x10
4947
5048
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir‎

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -19,9 +19,8 @@ body: |
1919
; CHECK-NEXT: $x10 = COPY [[FCVT_W_S]]
2020
; CHECK-NEXT: PseudoRET implicit $x10
2121
%0:fprb(s32) = COPY $f10_f
22-
%1:gprb(s32) = G_FPTOSI %0(s32)
23-
%2:gprb(s64) = G_ANYEXT %1(s32)
24-
$x10 = COPY %2(s64)
22+
%1:gprb(s64) = G_FCVT_W_RV64 %0(s32), 1
23+
$x10 = COPY %1(s64)
2524
PseudoRET implicit $x10
2625
2726
...
@@ -42,9 +41,8 @@ body: |
4241
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_S]]
4342
; CHECK-NEXT: PseudoRET implicit $x10
4443
%0:fprb(s32) = COPY $f10_f
45-
%1:gprb(s32) = G_FPTOUI %0(s32)
46-
%2:gprb(s64) = G_ANYEXT %1(s32)
47-
$x10 = COPY %2(s64)
44+
%1:gprb(s64) = G_FCVT_WU_RV64 %0(s32), 1
45+
$x10 = COPY %1(s64)
4846
PseudoRET implicit $x10
4947
5048
...
@@ -109,9 +107,8 @@ body: |
109107
; CHECK-NEXT: $x10 = COPY [[FCVT_W_D]]
110108
; CHECK-NEXT: PseudoRET implicit $x10
111109
%0:fprb(s64) = COPY $f10_d
112-
%1:gprb(s32) = G_FPTOSI %0(s64)
113-
%2:gprb(s64) = G_ANYEXT %1(s32)
114-
$x10 = COPY %2(s64)
110+
%1:gprb(s64) = G_FCVT_W_RV64 %0(s64), 1
111+
$x10 = COPY %1(s64)
115112
PseudoRET implicit $x10
116113
117114
...
@@ -132,9 +129,8 @@ body: |
132129
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_D]]
133130
; CHECK-NEXT: PseudoRET implicit $x10
134131
%0:fprb(s64) = COPY $f10_d
135-
%1:gprb(s32) = G_FPTOUI %0(s64)
136-
%2:gprb(s64) = G_ANYEXT %1(s32)
137-
$x10 = COPY %2(s64)
132+
%1:gprb(s64) = G_FCVT_WU_RV64 %0(s64), 1
133+
$x10 = COPY %1(s64)
138134
PseudoRET implicit $x10
139135
140136
...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir‎

Lines changed: 16 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,8 @@ body: |
1212
; CHECK: liveins: $f10_h
1313
; CHECK-NEXT: {{ $}}
1414
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
15-
; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
16-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
17-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
15+
; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1
16+
; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
1817
; CHECK-NEXT: PseudoRET implicit $x10
1918
%0:_(s16) = COPY $f10_h
2019
%1:_(s1) = G_FPTOSI %0(s16)
@@ -33,9 +32,8 @@ body: |
3332
; CHECK: liveins: $f10_h
3433
; CHECK-NEXT: {{ $}}
3534
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
36-
; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
37-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
38-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
35+
; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1
36+
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
3937
; CHECK-NEXT: PseudoRET implicit $x10
4038
%0:_(s16) = COPY $f10_h
4139
%1:_(s1) = G_FPTOUI %0(s16)
@@ -54,9 +52,8 @@ body: |
5452
; CHECK: liveins: $f10_h
5553
; CHECK-NEXT: {{ $}}
5654
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
57-
; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
58-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
59-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
55+
; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1
56+
; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
6057
; CHECK-NEXT: PseudoRET implicit $x10
6158
%0:_(s16) = COPY $f10_h
6259
%1:_(s8) = G_FPTOSI %0(s16)
@@ -75,9 +72,8 @@ body: |
7572
; CHECK: liveins: $f10_h
7673
; CHECK-NEXT: {{ $}}
7774
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
78-
; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
79-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
80-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
75+
; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1
76+
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
8177
; CHECK-NEXT: PseudoRET implicit $x10
8278
%0:_(s16) = COPY $f10_h
8379
%1:_(s8) = G_FPTOUI %0(s16)
@@ -96,9 +92,8 @@ body: |
9692
; CHECK: liveins: $f10_h
9793
; CHECK-NEXT: {{ $}}
9894
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
99-
; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
100-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
101-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
95+
; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1
96+
; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
10297
; CHECK-NEXT: PseudoRET implicit $x10
10398
%0:_(s16) = COPY $f10_h
10499
%1:_(s16) = G_FPTOSI %0(s16)
@@ -117,9 +112,8 @@ body: |
117112
; CHECK: liveins: $f10_h
118113
; CHECK-NEXT: {{ $}}
119114
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
120-
; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
121-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
122-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
115+
; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1
116+
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
123117
; CHECK-NEXT: PseudoRET implicit $x10
124118
%0:_(s16) = COPY $f10_h
125119
%1:_(s16) = G_FPTOUI %0(s16)
@@ -138,9 +132,8 @@ body: |
138132
; CHECK: liveins: $f10_h
139133
; CHECK-NEXT: {{ $}}
140134
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
141-
; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16)
142-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
143-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
135+
; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1
136+
; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64)
144137
; CHECK-NEXT: PseudoRET implicit $x10
145138
%0:_(s16) = COPY $f10_h
146139
%1:_(s32) = G_FPTOSI %0(s16)
@@ -159,9 +152,8 @@ body: |
159152
; CHECK: liveins: $f10_h
160153
; CHECK-NEXT: {{ $}}
161154
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
162-
; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16)
163-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
164-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
155+
; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1
156+
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64)
165157
; CHECK-NEXT: PseudoRET implicit $x10
166158
%0:_(s16) = COPY $f10_h
167159
%1:_(s32) = G_FPTOUI %0(s16)

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