Skip to content

Commit d345cfb

Browse files
topperctopperc
committed
[RISCV][GISel] Support s64 G_SELECT on RV32 with D extension.
We have to force the register bank to FPRB if the type is s64 and the GPR is 32 bits.
1 parent 5e7e0d6 commit d345cfb

File tree

5 files changed

+130
-34
lines changed

5 files changed

+130
-34
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -139,10 +139,12 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
139139
.clampScalar(1, sXLen, sXLen)
140140
.clampScalar(0, sXLen, sXLen);
141141

142-
getActionDefinitionsBuilder(G_SELECT)
143-
.legalFor({{sXLen, sXLen}, {s32, sXLen}, {p0, sXLen}})
144-
.widenScalarToNextPow2(0)
145-
.clampScalar(0, s32, sXLen)
142+
auto &SelectActions = getActionDefinitionsBuilder(G_SELECT).legalFor(
143+
{{s32, sXLen}, {p0, sXLen}});
144+
if (XLen == 64 || ST.hasStdExtD())
145+
SelectActions.legalFor({{s64, sXLen}});
146+
SelectActions.widenScalarToNextPow2(0)
147+
.clampScalar(0, s32, (XLen == 64 || ST.hasStdExtD()) ? s64 : s32)
146148
.clampScalar(1, sXLen, sXLen);
147149

148150
auto &LoadStoreActions =

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp‎

Lines changed: 35 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -332,37 +332,42 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
332332
// everything has to be on GPR.
333333
unsigned NumFP = 0;
334334

335-
// Check if the uses of the result always produce floating point values.
336-
//
337-
// For example:
338-
//
339-
// %z = G_SELECT %cond %x %y
340-
// fpr = G_FOO %z ...
341-
if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
342-
[&](const MachineInstr &UseMI) {
343-
return onlyUsesFP(UseMI, MRI, TRI);
344-
}))
345-
++NumFP;
346-
347-
// Check if the defs of the source values always produce floating point
348-
// values.
349-
//
350-
// For example:
351-
//
352-
// %x = G_SOMETHING_ALWAYS_FLOAT %a ...
353-
// %z = G_SELECT %cond %x %y
354-
//
355-
// Also check whether or not the sources have already been decided to be
356-
// FPR. Keep track of this.
357-
//
358-
// This doesn't check the condition, since the condition is always an
359-
// integer.
360-
for (unsigned Idx = 2; Idx < 4; ++Idx) {
361-
Register VReg = MI.getOperand(Idx).getReg();
362-
MachineInstr *DefMI = MRI.getVRegDef(VReg);
363-
if (getRegBank(VReg, MRI, TRI) == &RISCV::FPRBRegBank ||
364-
onlyDefinesFP(*DefMI, MRI, TRI))
335+
// Use FPR64 for s64 select on rv32.
336+
if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
337+
NumFP = 3;
338+
} else {
339+
// Check if the uses of the result always produce floating point values.
340+
//
341+
// For example:
342+
//
343+
// %z = G_SELECT %cond %x %y
344+
// fpr = G_FOO %z ...
345+
if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
346+
[&](const MachineInstr &UseMI) {
347+
return onlyUsesFP(UseMI, MRI, TRI);
348+
}))
365349
++NumFP;
350+
351+
// Check if the defs of the source values always produce floating point
352+
// values.
353+
//
354+
// For example:
355+
//
356+
// %x = G_SOMETHING_ALWAYS_FLOAT %a ...
357+
// %z = G_SELECT %cond %x %y
358+
//
359+
// Also check whether or not the sources have already been decided to be
360+
// FPR. Keep track of this.
361+
//
362+
// This doesn't check the condition, since the condition is always an
363+
// integer.
364+
for (unsigned Idx = 2; Idx < 4; ++Idx) {
365+
Register VReg = MI.getOperand(Idx).getReg();
366+
MachineInstr *DefMI = MRI.getVRegDef(VReg);
367+
if (getRegBank(VReg, MRI, TRI) == &RISCV::FPRBRegBank ||
368+
onlyDefinesFP(*DefMI, MRI, TRI))
369+
++NumFP;
370+
}
366371
}
367372

368373
// Condition operand is always GPR.

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv32.mir‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,3 +31,32 @@ body: |
3131
PseudoRET implicit $f10_f
3232
3333
...
34+
---
35+
name: fp_select_s64
36+
legalized: true
37+
regBankSelected: true
38+
tracksRegLiveness: true
39+
body: |
40+
bb.0.entry:
41+
liveins: $x10, $f10_d, $f11_d
42+
43+
; CHECK-LABEL: name: fp_select_s64
44+
; CHECK: liveins: $x10, $f10_d, $f11_d
45+
; CHECK-NEXT: {{ $}}
46+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
47+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f10_d
48+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f11_d
49+
; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
50+
; CHECK-NEXT: [[Select_FPR64_Using_CC_GPR:%[0-9]+]]:fpr64 = Select_FPR64_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]]
51+
; CHECK-NEXT: $f10_d = COPY [[Select_FPR64_Using_CC_GPR]]
52+
; CHECK-NEXT: PseudoRET implicit $f10_d
53+
%0:gprb(s32) = COPY $x10
54+
%1:fprb(s64) = COPY $f10_d
55+
%2:fprb(s64) = COPY $f11_d
56+
%3:gprb(s32) = G_CONSTANT i32 1
57+
%4:gprb(s32) = G_AND %0, %3
58+
%5:fprb(s64) = G_SELECT %4(s32), %1, %2
59+
$f10_d = COPY %5(s64)
60+
PseudoRET implicit $f10_d
61+
62+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-select-rv32.mir‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2+
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \
3+
# RUN: | FileCheck %s
4+
5+
---
6+
name: select_f64
7+
tracksRegLiveness: true
8+
body: |
9+
bb.1:
10+
liveins: $x10, $f10_d, $f11_d
11+
12+
; CHECK-LABEL: name: select_f64
13+
; CHECK: liveins: $x10, $f10_d, $f11_d
14+
; CHECK-NEXT: {{ $}}
15+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
16+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f10_d
17+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $f11_d
18+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
19+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
20+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
21+
; CHECK-NEXT: $f10_d = COPY [[SELECT]](s64)
22+
; CHECK-NEXT: PseudoRET implicit $f10_d
23+
%3:_(s32) = COPY $x10
24+
%0:_(s1) = G_TRUNC %3(s32)
25+
%1:_(s64) = COPY $f10_d
26+
%2:_(s64) = COPY $f11_d
27+
%4:_(s64) = G_SELECT %0(s1), %1, %2
28+
$f10_d = COPY %4(s64)
29+
PseudoRET implicit $f10_d
30+
31+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,35 @@ body: |
3131
$f10_f = COPY %10(s32)
3232
PseudoRET implicit $f10_f
3333
34+
...
35+
---
36+
name: fp_select_s64
37+
legalized: true
38+
tracksRegLiveness: true
39+
body: |
40+
bb.0.entry:
41+
liveins: $x10, $f10_d, $f11_d
42+
43+
; RV32I-LABEL: name: fp_select_s64
44+
; RV32I: liveins: $x10, $f10_d, $f11_d
45+
; RV32I-NEXT: {{ $}}
46+
; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
47+
; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
48+
; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d
49+
; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
50+
; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
51+
; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s64) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
52+
; RV32I-NEXT: $f10_d = COPY [[SELECT]](s64)
53+
; RV32I-NEXT: PseudoRET implicit $f10_d
54+
%3:_(s32) = COPY $x10
55+
%4:_(s64) = COPY $f10_d
56+
%5:_(s64) = COPY $f11_d
57+
%12:_(s32) = G_CONSTANT i32 1
58+
%11:_(s32) = G_AND %3, %12
59+
%10:_(s64) = G_SELECT %11(s32), %4, %5
60+
$f10_d = COPY %10(s64)
61+
PseudoRET implicit $f10_d
62+
3463
...
3564
---
3665
name: fp_select_gpr_use_s32

0 commit comments

Comments
 (0)