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[RISCV] Add MC layer support for Andes XAndesVSIntH extension. (#159514)
Add MC layer support for Andes XAndesVSIntH extension. The spec is available at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -165,6 +165,7 @@
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// CHECK-NEXT: xandesvbfhcvt 5.0 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)
166166
// CHECK-NEXT: xandesvdot 5.0 'XAndesVDot' (Andes Vector Dot Product Extension)
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// CHECK-NEXT: xandesvpackfph 5.0 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)
168+
// CHECK-NEXT: xandesvsinth 5.0 'XAndesVSIntH' (Andes Vector Small INT Handling Extension)
168169
// CHECK-NEXT: xandesvsintload 5.0 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)
169170
// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations)
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// CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching)

‎clang/test/Preprocessor/riscv-target-features-andes.c‎

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@@ -6,6 +6,7 @@
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// CHECK-NOT: __riscv_xandesperf {{.*$}}
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// CHECK-NOT: __riscv_xandesbfhcvt {{.*$}}
88
// CHECK-NOT: __riscv_xandesvbfhcvt {{.*$}}
9+
// CHECK-NOT: __riscv_xandesvsinth {{.*$}}
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// CHECK-NOT: __riscv_xandesvsintload {{.*$}}
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// CHECK-NOT: __riscv_xandesvpackfph {{.*$}}
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// CHECK-NOT: __riscv_xandesvdot {{.*$}}
@@ -34,6 +35,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s
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// CHECK-XANDESVBFHCVT: __riscv_xandesvbfhcvt 5000000{{$}}
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// RUN: %clang --target=riscv32 \
39+
// RUN: -march=rv32i_xandesvsinth -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVSINTH %s
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// RUN: %clang --target=riscv64 \
42+
// RUN: -march=rv64i_xandesvsinth -E -dM %s \
43+
// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVSINTH %s
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// CHECK-XANDESVSINTH: __riscv_xandesvsinth 5000000{{$}}
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// RUN: %clang --target=riscv32 \
3847
// RUN: -march=rv32i_xandesvsintload -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVSINTLOAD %s

‎llvm/docs/RISCVUsage.rst‎

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@@ -527,6 +527,9 @@ The current vendor extensions supported are:
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``XAndesVBFHCvt``
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LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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``XAndesVSINTH``
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LLVM implements `version 5.0.0 of the Andes Vector Small Int Handling Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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``XAndesVSINTLoad``
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LLVM implements `version 5.0.0 of the Andes Vector INT4 Load Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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‎llvm/docs/ReleaseNotes.md‎

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@@ -126,6 +126,7 @@ Changes to the RISC-V Backend
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* Add support for Zvfbfa (Additional BF16 vector compute support)
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* Adds experimental support for the 'Zibi` (Branch with Immediate) extension.
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* Add support for Zvfofp8min (OFP8 conversion extension)
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* Adds assembler support for the Andes `XAndesvsinth` (Andes Vector Small Int Handling Extension).
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -676,8 +676,8 @@ static constexpr FeatureBitset XTHeadGroup = {
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RISCV::FeatureVendorXTHeadVdot};
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static constexpr FeatureBitset XAndesGroup = {
679-
RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt,
680-
RISCV::FeatureVendorXAndesVBFHCvt,
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RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt,
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RISCV::FeatureVendorXAndesVBFHCvt, RISCV::FeatureVendorXAndesVSIntH,
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RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,
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RISCV::FeatureVendorXAndesVDot};
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‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1648,6 +1648,14 @@ def HasVendorXAndesVBFHCvt
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AssemblerPredicate<(all_of FeatureVendorXAndesVBFHCvt),
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"'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)">;
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def FeatureVendorXAndesVSIntH
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: RISCVExtension<5, 0, "Andes Vector Small INT Handling Extension",
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[FeatureStdExtZve32x]>;
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def HasVendorXAndesVSIntH
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: Predicate<"Subtarget->hasVendorXAndesVSIntH()">,
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AssemblerPredicate<(all_of FeatureVendorXAndesVSIntH),
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"'XAndesVSIntH' (Andes Vector Small INT Handling Extension)">;
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def FeatureVendorXAndesVSIntLoad
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: RISCVExtension<5, 0, "Andes Vector INT4 Load Extension",
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[FeatureStdExtZve32x]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td‎

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@@ -362,6 +362,47 @@ class NDSRVInstSDGP<bits<3> funct3, string opcodestr>
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let mayStore = 1;
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}
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class NDSRVInstVSINTLN<bits<5> funct5, string opcodestr>
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: RVInst<(outs VR:$vd), (ins GPRMemZeroOffset:$rs1),
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opcodestr, "$vd, ${rs1}", [], InstFormatR>,
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VLESchedMC {
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bits<5> rs1;
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bits<5> vd;
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let Inst{31-26} = 0b000001;
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let Inst{25} = 1;
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let Inst{24-20} = funct5;
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let Inst{19-15} = rs1;
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let Inst{14-12} = 0b100;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_CUSTOM_2.Value;
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let hasSideEffects = 0;
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let mayLoad = 1;
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let mayStore = 0;
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let Uses = [VTYPE, VL];
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}
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class NDSRVInstVSINTCvt<bits<5> fucnt5, string opcodestr>
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: RVInst<(outs VR:$vd), (ins VR:$vs, VMaskOp:$vm),
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opcodestr, "$vd, $vs$vm", [], InstFormatR> {
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bits<5> vs;
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bits<5> vd;
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bit vm;
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let Inst{31-26} = 0b000000;
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let Inst{25} = vm;
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let Inst{24-20} = vs;
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let Inst{19-15} = fucnt5;
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let Inst{14-12} = 0b100;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_CUSTOM_2.Value;
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let hasSideEffects = 0;
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let mayLoad = 0;
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let mayStore = 0;
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let Uses = [FRM, VL, VTYPE];
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let RVVConstraint = VMConstraint;
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}
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class NDSRVInstBFHCvt<bits<7> funct7, bits<5> rs1val, DAGOperand rdty,
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DAGOperand rs2ty, string opcodestr>
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: RVInstR<funct7, 0b100, OPC_CUSTOM_2, (outs rdty:$rd),
@@ -679,6 +720,18 @@ let Uses = [FRM, VL, VTYPE] in
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def NDS_VFNCVT_BF16_S : NDSRVInstVBFHCvt<0b00001, "nds.vfncvt.bf16.s">;
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}
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//===----------------------------------------------------------------------===//
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// XAndesVSIntH
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVendorXAndesVSIntH] in {
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def NDS_VFWCVT_F_N : NDSRVInstVSINTCvt<0b00100, "nds.vfwcvt.f.n.v">;
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def NDS_VFWCVT_F_NU : NDSRVInstVSINTCvt<0b00101, "nds.vfwcvt.f.nu.v">;
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def NDS_VFWCVT_F_B : NDSRVInstVSINTCvt<0b00110, "nds.vfwcvt.f.b.v">;
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def NDS_VFWCVT_F_BU : NDSRVInstVSINTCvt<0b00111, "nds.vfwcvt.f.bu.v">;
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def NDS_VLE4_V : NDSRVInstVSINTLN<0b00000, "nds.vle4.v">;
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}
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//===----------------------------------------------------------------------===//
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// XAndesVSIntLoad
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//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/attributes-andes.ll‎

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@@ -3,27 +3,31 @@
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; RUN: llc -mtriple=riscv32 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV32XANDESPERF %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESBFHCVT %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESVBFHCVT %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesvsinth %s -o - | FileCheck --check-prefix=RV32XANDESVSINTH %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesvsintload %s -o - | FileCheck --check-prefix=RV32XANDESVSINTLOAD %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV32XANDESVDOT %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV32XANDESVPACKFPH %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV64XANDESPERF %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESBFHCVT %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESVBFHCVT %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesvsinth %s -o - | FileCheck --check-prefix=RV64XANDESVSINTH %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesvsintload %s -o - | FileCheck --check-prefix=RV64XANDESVSINTLOAD %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV64XANDESVDOT %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV64XANDESVPACKFPH %s
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; RV32XANDESPERF: .attribute 5, "rv32i2p1_xandesperf5p0"
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; RV32XANDESBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"
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; RV32XANDESVBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0"
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; RV32XANDESVSINTH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsinth5p0"
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; RV32XANDESVSINTLOAD: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsintload5p0"
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; RV32XANDESVDOT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0"
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; RV32XANDESVPACKFPH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xandesvpackfph5p0"
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; RV64XANDESPERF: .attribute 5, "rv64i2p1_xandesperf5p0"
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; RV64XANDESBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"
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; RV64XANDESVBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0"
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; RV64XANDESVSINTH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsinth5p0"
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; RV64XANDESVSINTLOAD: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsintload5p0"
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; RV64XANDESVDOT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0"
2933
; RV64XANDESVPACKFPH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xandesvpackfph5p0"

‎llvm/test/CodeGen/RISCV/features-info.ll‎

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@@ -191,6 +191,7 @@
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; CHECK-NEXT: xandesvbfhcvt - 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension).
192192
; CHECK-NEXT: xandesvdot - 'XAndesVDot' (Andes Vector Dot Product Extension).
193193
; CHECK-NEXT: xandesvpackfph - 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension).
194+
; CHECK-NEXT: xandesvsinth - 'XAndesVSIntH' (Andes Vector Small INT Handling Extension).
194195
; CHECK-NEXT: xandesvsintload - 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension).
195196
; CHECK-NEXT: xcvalu - 'XCValu' (CORE-V ALU Operations).
196197
; CHECK-NEXT: xcvbi - 'XCVbi' (CORE-V Immediate Branching).

‎llvm/test/MC/RISCV/xandesvsinth-valid.s‎

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# XAndesVSIntLoad - Andes Vector INT4 Load Extension
2+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesvsinth -show-encoding \
3+
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
4+
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesvsinth < %s \
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# RUN: | llvm-objdump --mattr=+xandesvsinth -M no-aliases -d -r - \
6+
# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s
7+
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
8+
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
9+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+xandesvsinth -show-encoding \
10+
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xandesvsinth < %s \
12+
# RUN: | llvm-objdump --mattr=+xandesvsinth -M no-aliases -d -r - \
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# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s
14+
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
15+
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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# CHECK-OBJ: nds.vfwcvt.f.n.v v8, v10
17+
# CHECK-ASM: nds.vfwcvt.f.n.v v8, v10
18+
# CHECK-ASM: encoding: [0x5b,0x44,0xa2,0x02]
19+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
20+
nds.vfwcvt.f.n.v v8, v10
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# CHECK-OBJ: nds.vfwcvt.f.n.v v8, v10, v0.t
22+
# CHECK-ASM: nds.vfwcvt.f.n.v v8, v10, v0.t
23+
# CHECK-ASM: encoding: [0x5b,0x44,0xa2,0x00]
24+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
25+
nds.vfwcvt.f.n.v v8, v10, v0.t
26+
# CHECK-OBJ: nds.vfwcvt.f.nu.v v8, v10
27+
# CHECK-ASM: nds.vfwcvt.f.nu.v v8, v10
28+
# CHECK-ASM: encoding: [0x5b,0xc4,0xa2,0x02]
29+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
30+
nds.vfwcvt.f.nu.v v8, v10
31+
# CHECK-OBJ: nds.vfwcvt.f.nu.v v8, v10, v0.t
32+
# CHECK-ASM: nds.vfwcvt.f.nu.v v8, v10, v0.t
33+
# CHECK-ASM: encoding: [0x5b,0xc4,0xa2,0x00]
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# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
35+
nds.vfwcvt.f.nu.v v8, v10, v0.t
36+
# CHECK-OBJ: nds.vfwcvt.f.b.v v8, v10
37+
# CHECK-ASM: nds.vfwcvt.f.b.v v8, v10
38+
# CHECK-ASM: encoding: [0x5b,0x44,0xa3,0x02]
39+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
40+
nds.vfwcvt.f.b.v v8, v10
41+
# CHECK-OBJ: nds.vfwcvt.f.b.v v8, v10, v0.t
42+
# CHECK-ASM: nds.vfwcvt.f.b.v v8, v10, v0.t
43+
# CHECK-ASM: encoding: [0x5b,0x44,0xa3,0x00]
44+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
45+
nds.vfwcvt.f.b.v v8, v10, v0.t
46+
# CHECK-OBJ: nds.vfwcvt.f.bu.v v8, v10
47+
# CHECK-ASM: nds.vfwcvt.f.bu.v v8, v10
48+
# CHECK-ASM: encoding: [0x5b,0xc4,0xa3,0x02]
49+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
50+
nds.vfwcvt.f.bu.v v8, v10
51+
# CHECK-OBJ: nds.vfwcvt.f.bu.v v8, v10, v0.t
52+
# CHECK-ASM: nds.vfwcvt.f.bu.v v8, v10, v0.t
53+
# CHECK-ASM: encoding: [0x5b,0xc4,0xa3,0x00]
54+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
55+
nds.vfwcvt.f.bu.v v8, v10, v0.t
56+
# CHECK-OBJ: nds.vle4.v v8, (a0)
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# CHECK-ASM: nds.vle4.v v8, (a0)
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# CHECK-ASM: encoding: [0x5b,0x44,0x05,0x06]
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# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
60+
nds.vle4.v v8, (a0)

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