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Integrated and autogenerated test.
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir‎

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...
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---
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name: test_ashr_v4s1_v4s1
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; SI-LABEL: name: test_ashr_v4s1_v4s1
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; SI: liveins: $vgpr0, $vgpr1
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; SI-NEXT: {{ $}}
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; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
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; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
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; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
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; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
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; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
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; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
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; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
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; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
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; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
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; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C]]
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; SI-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 1
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; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
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; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C]]
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; SI-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 1
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; SI-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND2]](s32)
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; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C]]
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; SI-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 1
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; SI-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[AND3]](s32)
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; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
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; SI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
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; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
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; SI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C]]
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; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
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; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
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; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC1]]
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; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
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; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C]]
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; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[COPY3]](s32)
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; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
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; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC2]]
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; SI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
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; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C]]
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; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY4]](s32)
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; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
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; SI-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC3]]
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; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
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; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
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; SI-NEXT: $vgpr0 = COPY [[AND8]](s32)
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;
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; VI-LABEL: name: test_ashr_v4s1_v4s1
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; VI: liveins: $vgpr0, $vgpr1
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; VI-NEXT: {{ $}}
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; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
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; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
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; VI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
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; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
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; VI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
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; VI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
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; VI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
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; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
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; VI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
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; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
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; VI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
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; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
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; VI-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC1]], [[AND]](s16)
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; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
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; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
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; VI-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 1
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; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
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; VI-NEXT: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC3]], [[AND1]](s16)
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; VI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
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; VI-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C4]]
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; VI-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 1
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; VI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG2]](s32)
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; VI-NEXT: [[ASHR2:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC5]], [[AND2]](s16)
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; VI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
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; VI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C4]]
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; VI-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 1
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; VI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG3]](s32)
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; VI-NEXT: [[ASHR3:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC7]], [[AND3]](s16)
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; VI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[ASHR]], [[C4]]
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; VI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C4]]
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; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C4]](s16)
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; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL]]
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; VI-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[ASHR2]], [[C4]]
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; VI-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
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; VI-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND6]], [[C5]](s16)
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; VI-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[SHL1]]
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; VI-NEXT: [[AND7:%[0-9]+]]:_(s16) = G_AND [[ASHR3]], [[C4]]
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; VI-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 3
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; VI-NEXT: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C6]](s16)
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; VI-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[SHL2]]
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; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
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; VI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
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; VI-NEXT: $vgpr0 = COPY [[AND8]](s32)
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;
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; GFX9PLUS-LABEL: name: test_ashr_v4s1_v4s1
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; GFX9PLUS: liveins: $vgpr0, $vgpr1
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; GFX9PLUS-NEXT: {{ $}}
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; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; GFX9PLUS-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; GFX9PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; GFX9PLUS-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
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; GFX9PLUS-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
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; GFX9PLUS-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
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; GFX9PLUS-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
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; GFX9PLUS-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
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; GFX9PLUS-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
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; GFX9PLUS-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
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; GFX9PLUS-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
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; GFX9PLUS-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
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; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
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; GFX9PLUS-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
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; GFX9PLUS-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
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; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC1]], [[AND]](s16)
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; GFX9PLUS-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
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; GFX9PLUS-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
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; GFX9PLUS-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 1
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; GFX9PLUS-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
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; GFX9PLUS-NEXT: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC3]], [[AND1]](s16)
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; GFX9PLUS-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
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; GFX9PLUS-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C4]]
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; GFX9PLUS-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 1
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; GFX9PLUS-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG2]](s32)
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; GFX9PLUS-NEXT: [[ASHR2:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC5]], [[AND2]](s16)
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; GFX9PLUS-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
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; GFX9PLUS-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C4]]
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; GFX9PLUS-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 1
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; GFX9PLUS-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG3]](s32)
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; GFX9PLUS-NEXT: [[ASHR3:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC7]], [[AND3]](s16)
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; GFX9PLUS-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[ASHR]], [[C4]]
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; GFX9PLUS-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C4]]
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; GFX9PLUS-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C4]](s16)
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; GFX9PLUS-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL]]
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; GFX9PLUS-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[ASHR2]], [[C4]]
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; GFX9PLUS-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
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; GFX9PLUS-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND6]], [[C5]](s16)
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; GFX9PLUS-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[SHL1]]
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; GFX9PLUS-NEXT: [[AND7:%[0-9]+]]:_(s16) = G_AND [[ASHR3]], [[C4]]
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; GFX9PLUS-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 3
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; GFX9PLUS-NEXT: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C6]](s16)
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; GFX9PLUS-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[SHL2]]
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; GFX9PLUS-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
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; GFX9PLUS-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
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; GFX9PLUS-NEXT: $vgpr0 = COPY [[AND8]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s4) = G_TRUNC %0
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%3:_(s4) = G_TRUNC %1
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%4:_(<4 x s1>) = G_BITCAST %2
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%5:_(<4 x s1>) = G_BITCAST %3
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%6:_(<4 x s1>) = G_ASHR %4, %5
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%7:_(s4) = G_BITCAST %6
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%8:_(s32) = G_ZEXT %7
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$vgpr0 = COPY %8
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...
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---
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name: test_ashr_v4s16_v4s16
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body: |
@@ -2258,3 +2428,7 @@ body: |
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%6:_(s96) = G_ANYEXT %5
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$vgpr0_vgpr1_vgpr2 = COPY %6
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...
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## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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# GFX9PLUS: {{.*}}
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# SI: {{.*}}
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# VI: {{.*}}

‎llvm/test/CodeGen/AMDGPU/widen-vector-shift.ll‎

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