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spallspall
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update firstbithigh to the correct behavior. both dxil and spirv support 16, 32, and 64 bit now.
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11 files changed

+346
-100
lines changed

11 files changed

+346
-100
lines changed

‎clang/lib/CodeGen/CGBuiltin.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18742,7 +18742,7 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID,
1874218742
Value *X = EmitScalarExpr(E->getArg(0));
1874318743

1874418744
return Builder.CreateIntrinsic(
18745-
/*ReturnType=*/X->getType(),
18745+
/*ReturnType=*/ConvertType(E->getType()),
1874618746
getFirstBitHighIntrinsic(CGM.getHLSLRuntime(), E->getArg(0)->getType()),
1874718747
ArrayRef<Value *>{X}, nullptr, "hlsl.firstbithigh");
1874818748
}

‎clang/lib/Headers/hlsl/hlsl_intrinsics.h‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -970,38 +970,38 @@ float4 exp2(float4);
970970
#ifdef __HLSL_ENABLE_16_BIT
971971
_HLSL_AVAILABILITY(shadermodel, 6.2)
972972
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
973-
int16_t firstbithigh(int16_t);
973+
uint firstbithigh(int16_t);
974974
_HLSL_AVAILABILITY(shadermodel, 6.2)
975975
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
976-
int16_t2 firstbithigh(int16_t2);
976+
uint2 firstbithigh(int16_t2);
977977
_HLSL_AVAILABILITY(shadermodel, 6.2)
978978
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
979-
int16_t3 firstbithigh(int16_t3);
979+
uint3 firstbithigh(int16_t3);
980980
_HLSL_AVAILABILITY(shadermodel, 6.2)
981981
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
982-
int16_t4 firstbithigh(int16_t4);
982+
uint4 firstbithigh(int16_t4);
983983
_HLSL_AVAILABILITY(shadermodel, 6.2)
984984
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
985-
uint16_t firstbithigh(uint16_t);
985+
uint firstbithigh(uint16_t);
986986
_HLSL_AVAILABILITY(shadermodel, 6.2)
987987
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
988-
uint16_t2 firstbithigh(uint16_t2);
988+
uint2 firstbithigh(uint16_t2);
989989
_HLSL_AVAILABILITY(shadermodel, 6.2)
990990
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
991-
uint16_t3 firstbithigh(uint16_t3);
991+
uint3 firstbithigh(uint16_t3);
992992
_HLSL_AVAILABILITY(shadermodel, 6.2)
993993
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
994-
uint16_t4 firstbithigh(uint16_t4);
994+
uint4 firstbithigh(uint16_t4);
995995
#endif
996996

997997
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
998-
int firstbithigh(int);
998+
uint firstbithigh(int);
999999
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
1000-
int2 firstbithigh(int2);
1000+
uint2 firstbithigh(int2);
10011001
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
1002-
int3 firstbithigh(int3);
1002+
uint3 firstbithigh(int3);
10031003
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
1004-
int4 firstbithigh(int4);
1004+
uint4 firstbithigh(int4);
10051005

10061006
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
10071007
uint firstbithigh(uint);
@@ -1013,22 +1013,22 @@ _HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
10131013
uint4 firstbithigh(uint4);
10141014

10151015
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
1016-
int64_t firstbithigh(int64_t);
1016+
uint firstbithigh(int64_t);
10171017
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
1018-
int64_t2 firstbithigh(int64_t2);
1018+
uint2 firstbithigh(int64_t2);
10191019
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
1020-
int64_t3 firstbithigh(int64_t3);
1020+
uint3 firstbithigh(int64_t3);
10211021
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
1022-
int64_t4 firstbithigh(int64_t4);
1022+
uint4 firstbithigh(int64_t4);
10231023

10241024
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
1025-
uint64_t firstbithigh(uint64_t);
1025+
uint firstbithigh(uint64_t);
10261026
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
1027-
uint64_t2 firstbithigh(uint64_t2);
1027+
uint2 firstbithigh(uint64_t2);
10281028
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
1029-
uint64_t3 firstbithigh(uint64_t3);
1029+
uint3 firstbithigh(uint64_t3);
10301030
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_firstbithigh)
1031-
uint64_t4 firstbithigh(uint64_t4);
1031+
uint4 firstbithigh(uint64_t4);
10321032

10331033
//===----------------------------------------------------------------------===//
10341034
// floor builtins

‎clang/lib/Sema/SemaHLSL.cpp‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1898,16 +1898,20 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
18981898
QualType ArgTy = Arg->getType();
18991899
QualType EltTy = ArgTy;
19001900

1901-
if (auto *VecTy = EltTy->getAs<VectorType>())
1901+
QualType ResTy = SemaRef.Context.UnsignedIntTy;
1902+
1903+
if (auto *VecTy = EltTy->getAs<VectorType>()) {
19021904
EltTy = VecTy->getElementType();
1905+
ResTy = SemaRef.Context.getVectorType(ResTy, VecTy->getNumElements(), VecTy->getVectorKind());
1906+
}
19031907

19041908
if (!EltTy->isIntegerType()) {
19051909
Diag(Arg->getBeginLoc(), diag::err_builtin_invalid_arg_type)
19061910
<< 1 << /* integer ty */ 6 << ArgTy;
19071911
return true;
19081912
}
19091913

1910-
TheCall->setType(ArgTy);
1914+
TheCall->setType(ResTy);
19111915
break;
19121916
}
19131917
case Builtin::BI__builtin_hlsl_select: {

‎clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl‎

Lines changed: 36 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -8,50 +8,50 @@
88

99
#ifdef __HLSL_ENABLE_16_BIT
1010
// CHECK-LABEL: test_firstbithigh_ushort
11-
// CHECK: call i16 @llvm.[[TARGET]].firstbituhigh.i16
12-
int test_firstbithigh_ushort(uint16_t p0) {
11+
// CHECK: call i32 @llvm.[[TARGET]].firstbituhigh.i16
12+
uint test_firstbithigh_ushort(uint16_t p0) {
1313
return firstbithigh(p0);
1414
}
1515

1616
// CHECK-LABEL: test_firstbithigh_ushort2
17-
// CHECK: call <2 x i16> @llvm.[[TARGET]].firstbituhigh.v2i16
18-
uint16_t2 test_firstbithigh_ushort2(uint16_t2 p0) {
17+
// CHECK: call <2 x i32> @llvm.[[TARGET]].firstbituhigh.v2i16
18+
uint2 test_firstbithigh_ushort2(uint16_t2 p0) {
1919
return firstbithigh(p0);
2020
}
2121

2222
// CHECK-LABEL: test_firstbithigh_ushort3
23-
// CHECK: call <3 x i16> @llvm.[[TARGET]].firstbituhigh.v3i16
24-
uint16_t3 test_firstbithigh_ushort3(uint16_t3 p0) {
23+
// CHECK: call <3 x i32> @llvm.[[TARGET]].firstbituhigh.v3i16
24+
uint3 test_firstbithigh_ushort3(uint16_t3 p0) {
2525
return firstbithigh(p0);
2626
}
2727

2828
// CHECK-LABEL: test_firstbithigh_ushort4
29-
// CHECK: call <4 x i16> @llvm.[[TARGET]].firstbituhigh.v4i16
30-
uint16_t4 test_firstbithigh_ushort4(uint16_t4 p0) {
29+
// CHECK: call <4 x i32> @llvm.[[TARGET]].firstbituhigh.v4i16
30+
uint4 test_firstbithigh_ushort4(uint16_t4 p0) {
3131
return firstbithigh(p0);
3232
}
3333

3434
// CHECK-LABEL: test_firstbithigh_short
35-
// CHECK: call i16 @llvm.[[TARGET]].firstbitshigh.i16
36-
int16_t test_firstbithigh_short(int16_t p0) {
35+
// CHECK: call i32 @llvm.[[TARGET]].firstbitshigh.i16
36+
uint test_firstbithigh_short(int16_t p0) {
3737
return firstbithigh(p0);
3838
}
3939

4040
// CHECK-LABEL: test_firstbithigh_short2
41-
// CHECK: call <2 x i16> @llvm.[[TARGET]].firstbitshigh.v2i16
42-
int16_t2 test_firstbithigh_short2(int16_t2 p0) {
41+
// CHECK: call <2 x i32> @llvm.[[TARGET]].firstbitshigh.v2i16
42+
uint2 test_firstbithigh_short2(int16_t2 p0) {
4343
return firstbithigh(p0);
4444
}
4545

4646
// CHECK-LABEL: test_firstbithigh_short3
47-
// CHECK: call <3 x i16> @llvm.[[TARGET]].firstbitshigh.v3i16
48-
int16_t3 test_firstbithigh_short3(int16_t3 p0) {
47+
// CHECK: call <3 x i32> @llvm.[[TARGET]].firstbitshigh.v3i16
48+
uint3 test_firstbithigh_short3(int16_t3 p0) {
4949
return firstbithigh(p0);
5050
}
5151

5252
// CHECK-LABEL: test_firstbithigh_short4
53-
// CHECK: call <4 x i16> @llvm.[[TARGET]].firstbitshigh.v4i16
54-
int16_t4 test_firstbithigh_short4(int16_t4 p0) {
53+
// CHECK: call <4 x i32> @llvm.[[TARGET]].firstbitshigh.v4i16
54+
uint4 test_firstbithigh_short4(int16_t4 p0) {
5555
return firstbithigh(p0);
5656
}
5757
#endif // __HLSL_ENABLE_16_BIT
@@ -81,73 +81,73 @@ uint4 test_firstbithigh_uint4(uint4 p0) {
8181
}
8282

8383
// CHECK-LABEL: test_firstbithigh_ulong
84-
// CHECK: call i64 @llvm.[[TARGET]].firstbituhigh.i64
85-
uint64_t test_firstbithigh_ulong(uint64_t p0) {
84+
// CHECK: call i32 @llvm.[[TARGET]].firstbituhigh.i64
85+
uint test_firstbithigh_ulong(uint64_t p0) {
8686
return firstbithigh(p0);
8787
}
8888

8989
// CHECK-LABEL: test_firstbithigh_ulong2
90-
// CHECK: call <2 x i64> @llvm.[[TARGET]].firstbituhigh.v2i64
91-
uint64_t2 test_firstbithigh_ulong2(uint64_t2 p0) {
90+
// CHECK: call <2 x i32> @llvm.[[TARGET]].firstbituhigh.v2i64
91+
uint2 test_firstbithigh_ulong2(uint64_t2 p0) {
9292
return firstbithigh(p0);
9393
}
9494

9595
// CHECK-LABEL: test_firstbithigh_ulong3
96-
// CHECK: call <3 x i64> @llvm.[[TARGET]].firstbituhigh.v3i64
97-
uint64_t3 test_firstbithigh_ulong3(uint64_t3 p0) {
96+
// CHECK: call <3 x i32> @llvm.[[TARGET]].firstbituhigh.v3i64
97+
uint3 test_firstbithigh_ulong3(uint64_t3 p0) {
9898
return firstbithigh(p0);
9999
}
100100

101101
// CHECK-LABEL: test_firstbithigh_ulong4
102-
// CHECK: call <4 x i64> @llvm.[[TARGET]].firstbituhigh.v4i64
103-
uint64_t4 test_firstbithigh_ulong4(uint64_t4 p0) {
102+
// CHECK: call <4 x i32> @llvm.[[TARGET]].firstbituhigh.v4i64
103+
uint4 test_firstbithigh_ulong4(uint64_t4 p0) {
104104
return firstbithigh(p0);
105105
}
106106

107107
// CHECK-LABEL: test_firstbithigh_int
108108
// CHECK: call i32 @llvm.[[TARGET]].firstbitshigh.i32
109-
int test_firstbithigh_int(int p0) {
109+
uint test_firstbithigh_int(int p0) {
110110
return firstbithigh(p0);
111111
}
112112

113113
// CHECK-LABEL: test_firstbithigh_int2
114114
// CHECK: call <2 x i32> @llvm.[[TARGET]].firstbitshigh.v2i32
115-
int2 test_firstbithigh_int2(int2 p0) {
115+
uint2 test_firstbithigh_int2(int2 p0) {
116116
return firstbithigh(p0);
117117
}
118118

119119
// CHECK-LABEL: test_firstbithigh_int3
120120
// CHECK: call <3 x i32> @llvm.[[TARGET]].firstbitshigh.v3i32
121-
int3 test_firstbithigh_int3(int3 p0) {
121+
uint3 test_firstbithigh_int3(int3 p0) {
122122
return firstbithigh(p0);
123123
}
124124

125125
// CHECK-LABEL: test_firstbithigh_int4
126126
// CHECK: call <4 x i32> @llvm.[[TARGET]].firstbitshigh.v4i32
127-
int4 test_firstbithigh_int4(int4 p0) {
127+
uint4 test_firstbithigh_int4(int4 p0) {
128128
return firstbithigh(p0);
129129
}
130130

131131
// CHECK-LABEL: test_firstbithigh_long
132-
// CHECK: call i64 @llvm.[[TARGET]].firstbitshigh.i64
133-
int64_t test_firstbithigh_long(int64_t p0) {
132+
// CHECK: call i32 @llvm.[[TARGET]].firstbitshigh.i64
133+
uint test_firstbithigh_long(int64_t p0) {
134134
return firstbithigh(p0);
135135
}
136136

137137
// CHECK-LABEL: test_firstbithigh_long2
138-
// CHECK: call <2 x i64> @llvm.[[TARGET]].firstbitshigh.v2i64
139-
int64_t2 test_firstbithigh_long2(int64_t2 p0) {
138+
// CHECK: call <2 x i32> @llvm.[[TARGET]].firstbitshigh.v2i64
139+
uint2 test_firstbithigh_long2(int64_t2 p0) {
140140
return firstbithigh(p0);
141141
}
142142

143143
// CHECK-LABEL: test_firstbithigh_long3
144-
// CHECK: call <3 x i64> @llvm.[[TARGET]].firstbitshigh.v3i64
145-
int64_t3 test_firstbithigh_long3(int64_t3 p0) {
144+
// CHECK: call <3 x i32> @llvm.[[TARGET]].firstbitshigh.v3i64
145+
uint3 test_firstbithigh_long3(int64_t3 p0) {
146146
return firstbithigh(p0);
147147
}
148148

149149
// CHECK-LABEL: test_firstbithigh_long4
150-
// CHECK: call <4 x i64> @llvm.[[TARGET]].firstbitshigh.v4i64
151-
int64_t4 test_firstbithigh_long4(int64_t4 p0) {
150+
// CHECK: call <4 x i32> @llvm.[[TARGET]].firstbitshigh.v4i64
151+
uint4 test_firstbithigh_long4(int64_t4 p0) {
152152
return firstbithigh(p0);
153153
}

‎llvm/include/llvm/IR/IntrinsicsDirectX.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -90,6 +90,6 @@ def int_dx_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0
9090
def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
9191
def int_dx_step : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty, LLVMMatchType<0>], [IntrNoMem]>;
9292
def int_dx_radians : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
93-
def int_dx_firstbituhigh : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
94-
def int_dx_firstbitshigh : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
93+
def int_dx_firstbituhigh : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_anyint_ty], [IntrNoMem]>;
94+
def int_dx_firstbitshigh : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_anyint_ty], [IntrNoMem]>;
9595
}

‎llvm/include/llvm/IR/IntrinsicsSPIRV.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,6 @@ let TargetPrefix = "spv" in {
9797
[llvm_any_ty],
9898
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty],
9999
[IntrNoMem]>;
100-
def int_spv_firstbituhigh : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
101-
def int_spv_firstbitshigh : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
100+
def int_spv_firstbituhigh : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_anyint_ty], [IntrNoMem]>;
101+
def int_spv_firstbitshigh : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_anyint_ty], [IntrNoMem]>;
102102
}

‎llvm/lib/Target/DirectX/DXIL.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -564,24 +564,24 @@ def CBits : DXILOp<31, unary> {
564564
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
565565
}
566566

567-
def FirstbitHi : DXILOp<33, unaryBits> {
567+
def FirstbitHi : DXILOp<33, unary> {
568568
let Doc = "Returns the location of the first set bit starting from "
569569
"the highest order bit and working downward.";
570570
let LLVMIntrinsic = int_dx_firstbituhigh;
571571
let arguments = [OverloadTy];
572-
let result = OverloadTy;
572+
let result = Int32Ty;
573573
let overloads =
574574
[Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
575575
let stages = [Stages<DXIL1_0, [all_stages]>];
576576
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
577577
}
578578

579-
def FirstbitSHi : DXILOp<34, unaryBits> {
579+
def FirstbitSHi : DXILOp<34, unary> {
580580
let Doc = "Returns the location of the first set bit from "
581581
"the highest order bit based on the sign.";
582582
let LLVMIntrinsic = int_dx_firstbitshigh;
583583
let arguments = [OverloadTy];
584-
let result = OverloadTy;
584+
let result = Int32Ty;
585585
let overloads =
586586
[Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
587587
let stages = [Stages<DXIL1_0, [all_stages]>];

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -424,7 +424,7 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
424424
LLT LLTy = LLT::scalar(64);
425425
Register SpvVecConst =
426426
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
427-
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
427+
CurMF->getRegInfo().setRegClass(SpvVecConst, getRegClass(SpvType));
428428
assignSPIRVTypeToVReg(SpvType, SpvVecConst, *CurMF);
429429
DT.add(CA, CurMF, SpvVecConst);
430430
MachineInstrBuilder MIB;

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