@@ -2617,20 +2617,19 @@ defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, SchedWriteFCmp>, E
26172617multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
26182618 string OpcodeStr, RegisterClass KRC, ValueType vvt,
26192619 X86MemOperand x86memop, string Suffix = ""> {
2620- let explicitOpPrefix = !if(!eq(Suffix, ""), NoExplicitOpPrefix, ExplicitEVEX) in {
2621- let isMoveReg = 1, hasSideEffects = 0, SchedRW = [WriteMove] in
2622- def kk#Suffix : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2623- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
2624- Sched<[WriteMove]>;
2625- def km#Suffix : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
2626- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2627- [(set KRC:$dst, (vvt (load addr:$src)))]>,
2628- Sched<[WriteLoad]>, NoCD8;
2629- def mk#Suffix : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
2630- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2631- [(store KRC:$src, addr:$dst)]>,
2632- Sched<[WriteStore]>, NoCD8;
2633- }
2620+ let isMoveReg = 1, hasSideEffects = 0, SchedRW = [WriteMove],
2621+ explicitOpPrefix = !if(!eq(Suffix, ""), NoExplicitOpPrefix, ExplicitEVEX) in
2622+ def kk#Suffix : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2623+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
2624+ Sched<[WriteMove]>;
2625+ def km#Suffix : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
2626+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2627+ [(set KRC:$dst, (vvt (load addr:$src)))]>,
2628+ Sched<[WriteLoad]>, NoCD8;
2629+ def mk#Suffix : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
2630+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2631+ [(store KRC:$src, addr:$dst)]>,
2632+ Sched<[WriteStore]>, NoCD8;
26342633}
26352634
26362635multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
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