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RolandF77RolandF77
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lower vp load/store
1 parent 9fc353e commit d451b76

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4 files changed

+128
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4 files changed

+128
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‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 88 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -652,6 +652,15 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
652652
setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
653653
setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
654654

655+
setOperationAction(ISD::VP_STORE, MVT::v16i1, Custom);
656+
setOperationAction(ISD::VP_STORE, MVT::v8i1, Custom);
657+
setOperationAction(ISD::VP_STORE, MVT::v4i1, Custom);
658+
setOperationAction(ISD::VP_STORE, MVT::v2i1, Custom);
659+
setOperationAction(ISD::VP_LOAD, MVT::v16i1, Custom);
660+
setOperationAction(ISD::VP_LOAD, MVT::v8i1, Custom);
661+
setOperationAction(ISD::VP_LOAD, MVT::v4i1, Custom);
662+
setOperationAction(ISD::VP_LOAD, MVT::v2i1, Custom);
663+
655664
// We want to custom lower some of our intrinsics.
656665
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
657666
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f64, Custom);
@@ -11909,6 +11918,81 @@ SDValue PPCTargetLowering::LowerIS_FPCLASS(SDValue Op,
1190911918
return getDataClassTest(LHS, Category, Dl, DAG, Subtarget);
1191011919
}
1191111920

11921+
static SDValue AdjustLength(SDValue Val, unsigned Bits, bool Left,
11922+
SelectionDAG &DAG) {
11923+
SDLoc dl(Val);
11924+
EVT VT = Val->getValueType(0);
11925+
unsigned LeftAdj = Left ? VT.getSizeInBits() - 8 : 0;
11926+
unsigned TypeAdj = llvm::countr_zero<uint32_t>(Bits / 8);
11927+
// unsigned Shift = llvm::countr_zero<uint64_t>(Imm);
11928+
// EVT ShiftAmountTy = getShiftAmountTy(VT, DAG.getDataLayout());
11929+
// if (Value > 0 && isPowerOf2_64(Value))
11930+
SDValue SHLAmt = DAG.getConstant(LeftAdj + TypeAdj, dl, VT);
11931+
return DAG.getNode(ISD::SHL, dl, VT, Val, SHLAmt);
11932+
}
11933+
11934+
SDValue PPCTargetLowering::LowerVP_LOAD(SDValue Op, SelectionDAG &DAG) const {
11935+
dbgs() << "&&& Lower VP_LOAD\n";
11936+
Op.dump();
11937+
auto VPLD = cast<VPLoadSDNode>(Op);
11938+
bool Future = Subtarget.isISAFuture();
11939+
SDLoc dl(Op);
11940+
assert(ISD::isConstantSplatVectorAllOnes(Op->getOperand(3).getNode(), true) &&
11941+
"Mask predication not supported");
11942+
EVT PtrVT = getPointerTy(DAG.getDataLayout());
11943+
SDValue Len = DAG.getNode(ISD::ANY_EXTEND, dl, PtrVT, VPLD->getOperand(4));
11944+
unsigned IID = Future ? Intrinsic::ppc_vsx_lxvrl : Intrinsic::ppc_vsx_lxvl;
11945+
unsigned EltBits = Op->getValueType(0).getScalarType().getSizeInBits();
11946+
Len = AdjustLength(Len, EltBits, !Future, DAG);
11947+
SDValue Ops[] = {
11948+
VPLD->getChain(), // Chain
11949+
// DAG.getConstant(Intrinsic::ppc_vsx_lxvl, dl, MVT::i32),
11950+
DAG.getConstant(IID, dl, MVT::i32),
11951+
VPLD->getOperand(1),
11952+
// VPLD->getOperand(4),
11953+
// DAG.getNode(ISD::ANY_EXTEND, dl, PtrVT, VPLD->getOperand(4)),
11954+
Len
11955+
};
11956+
SDVTList Tys = DAG.getVTList(Op->getValueType(0), MVT::Other);
11957+
SDValue VPL = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl, Tys,
11958+
Ops, VPLD->getMemoryVT(), VPLD->getMemOperand());
11959+
VPL.dump();
11960+
return VPL;
11961+
// return SDValue();
11962+
}
11963+
11964+
SDValue PPCTargetLowering::LowerVP_STORE(SDValue Op, SelectionDAG &DAG) const {
11965+
dbgs() << "&&& Lower VP_STORE\n";
11966+
Op.dump();
11967+
auto VPST = cast<VPStoreSDNode>(Op);
11968+
assert(ISD::isConstantSplatVectorAllOnes(Op->getOperand(4).getNode(), true) &&
11969+
"Mask predication not supported");
11970+
EVT PtrVT = getPointerTy(DAG.getDataLayout());
11971+
SDLoc dl(Op);
11972+
SDValue Len = DAG.getNode(ISD::ANY_EXTEND, dl, PtrVT, VPST->getOperand(5));
11973+
unsigned EltBits = Op->getOperand(1).getValueType().getScalarType().getSizeInBits();
11974+
bool Future = Subtarget.isISAFuture();
11975+
unsigned IID = Future ? Intrinsic::ppc_vsx_stxvrl : Intrinsic::ppc_vsx_stxvl;
11976+
Len = AdjustLength(Len, EltBits, !Future, DAG);
11977+
SDValue Ops[] = {
11978+
VPST->getChain(), // Chain
11979+
// DAG.getConstant(Intrinsic::ppc_vsx_stxvl, dl, MVT::i32),
11980+
DAG.getConstant(IID, dl, MVT::i32),
11981+
// DAG.getTargetConstant(Intrinsic::ppc_vsx_stxvl, dl, MVT::i64),
11982+
DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, VPST->getOperand(1)),
11983+
VPST->getOperand(2),
11984+
// DAG.getNode(ISD::ANY_EXTEND, dl, PtrVT, VPST->getOperand(5)),
11985+
Len
11986+
};
11987+
SDVTList Tys = DAG.getVTList(MVT::Other);
11988+
// SDValue VPS = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl, Tys,
11989+
SDValue VPS = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, dl, Tys,
11990+
Ops, VPST->getMemoryVT(), VPST->getMemOperand());
11991+
VPS.dump();
11992+
return VPS;
11993+
// return SDValue();
11994+
}
11995+
1191211996
SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
1191311997
SelectionDAG &DAG) const {
1191411998
SDLoc dl(Op);
@@ -12763,6 +12847,10 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1276312847
if (Op->getFlags().hasNoFPExcept())
1276412848
return Op;
1276512849
return SDValue();
12850+
case ISD::VP_LOAD:
12851+
return LowerVP_LOAD(Op, DAG);
12852+
case ISD::VP_STORE:
12853+
return LowerVP_STORE(Op, DAG);
1276612854
}
1276712855
}
1276812856

‎llvm/lib/Target/PowerPC/PPCISelLowering.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1345,6 +1345,9 @@ namespace llvm {
13451345
SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
13461346
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
13471347

1348+
SDValue LowerVP_LOAD(SDValue Op, SelectionDAG &DAG) const;
1349+
SDValue LowerVP_STORE(SDValue Op, SelectionDAG &DAG) const;
1350+
13481351
SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
13491352
SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
13501353
SDValue LowerDMFVectorLoad(SDValue Op, SelectionDAG &DAG) const;

‎llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1031,3 +1031,37 @@ bool PPCTTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst,
10311031
bool PPCTTIImpl::supportsTailCallFor(const CallBase *CB) const {
10321032
return TLI->supportsTailCallFor(CB);
10331033
}
1034+
1035+
TargetTransformInfo::VPLegalization
1036+
PPCTTIImpl::getVPLegalizationStrategy(const VPIntrinsic &PI) const {
1037+
using VPLegalization = TargetTransformInfo::VPLegalization;
1038+
unsigned Directive = ST->getCPUDirective();
1039+
VPLegalization DefaultLegalization = BaseT::getVPLegalizationStrategy(PI);
1040+
if (Directive != PPC::DIR_PWR10 && Directive != PPC::DIR_PWR_FUTURE)
1041+
return DefaultLegalization;
1042+
1043+
unsigned IID = PI.getIntrinsicID();
1044+
if (IID != Intrinsic::vp_load && IID != Intrinsic::vp_store)
1045+
return DefaultLegalization;
1046+
1047+
bool IsLoad = IID == Intrinsic::vp_load;
1048+
Type* VecTy = IsLoad ? PI.getType() : PI.getOperand(0)->getType();
1049+
EVT VT = TLI->getValueType(DL, VecTy, true);
1050+
dbgs() << "&&& Typecheck " << VT << "\n";
1051+
if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
1052+
VT != MVT::v16i8)
1053+
return DefaultLegalization;
1054+
1055+
auto IsAllTrueMask = [](Value *MaskVal) {
1056+
if (Value *SplattedVal = getSplatValue(MaskVal))
1057+
if (auto *ConstValue = dyn_cast<Constant>(SplattedVal))
1058+
return ConstValue->isAllOnesValue();
1059+
return false;
1060+
};
1061+
unsigned MaskIx = IsLoad ? 1 : 2;
1062+
if (!IsAllTrueMask(PI.getOperand(MaskIx)))
1063+
return DefaultLegalization;
1064+
1065+
return VPLegalization(VPLegalization::Legal, VPLegalization::Legal);
1066+
}
1067+

‎llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -150,6 +150,9 @@ class PPCTTIImpl final : public BasicTTIImplBase<PPCTTIImpl> {
150150
const ArrayRef<Type *> &Types) const override;
151151
bool supportsTailCallFor(const CallBase *CB) const override;
152152

153+
TargetTransformInfo::VPLegalization
154+
getVPLegalizationStrategy(const VPIntrinsic &PI) const override;
155+
153156
private:
154157
// The following constant is used for estimating costs on power9.
155158
static const InstructionCost::CostType P9PipelineFlushEstimate = 80;

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