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mikhailramalhomikhailramalho
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[RISCV][VLOPT] Added support for several vector crypto instructions (#153071)
This PR adds support for the following instructions to the RISC-V VLOptimizer: vandn.vx, vandn.vv, vbrev.v, vclz.v, vcpop.v, vctz.v, vror.vi, vror.vx, vror.vv, vrol.vx, vrol.vv.
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+54
-28
lines changed

2 files changed

+54
-28
lines changed

‎llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp‎

Lines changed: 43 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -491,8 +491,31 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
491491
// vfirst find-first-set mask bit
492492
case RISCV::VCPOP_M:
493493
case RISCV::VFIRST_M:
494+
// Vector Bit-manipulation Instructions (Zvbb)
495+
// Vector And-Not
496+
case RISCV::VANDN_VV:
497+
case RISCV::VANDN_VX:
498+
// Vector Reverse Bits in Elements
499+
case RISCV::VBREV_V:
500+
// Vector Count Leading Zeros
501+
case RISCV::VCLZ_V:
502+
// Vector Count Trailing Zeros
503+
case RISCV::VCTZ_V:
504+
// Vector Population Count
505+
case RISCV::VCPOP_V:
506+
// Vector Rotate Left
507+
case RISCV::VROL_VV:
508+
case RISCV::VROL_VX:
509+
// Vector Rotate Right
510+
case RISCV::VROR_VI:
511+
case RISCV::VROR_VV:
512+
case RISCV::VROR_VX:
494513
return MILog2SEW;
495514

515+
// Vector Widening Shift Left Logical (Zvbb)
516+
case RISCV::VWSLL_VI:
517+
case RISCV::VWSLL_VX:
518+
case RISCV::VWSLL_VV:
496519
// Vector Widening Integer Add/Subtract
497520
// Def uses EEW=2*SEW . Operands use EEW=SEW.
498521
case RISCV::VWADDU_VV:
@@ -503,9 +526,6 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
503526
case RISCV::VWADD_VX:
504527
case RISCV::VWSUB_VV:
505528
case RISCV::VWSUB_VX:
506-
case RISCV::VWSLL_VI:
507-
case RISCV::VWSLL_VX:
508-
case RISCV::VWSLL_VV:
509529
// Vector Widening Integer Multiply Instructions
510530
// Destination EEW=2*SEW. Source EEW=SEW.
511531
case RISCV::VWMUL_VV:
@@ -1020,12 +1040,29 @@ static bool isSupportedInstr(const MachineInstr &MI) {
10201040
case RISCV::VNCLIP_WV:
10211041
case RISCV::VNCLIP_WX:
10221042
case RISCV::VNCLIP_WI:
1023-
1024-
// Vector Crypto
1043+
// Vector Bit-manipulation Instructions (Zvbb)
1044+
// Vector And-Not
1045+
case RISCV::VANDN_VV:
1046+
case RISCV::VANDN_VX:
1047+
// Vector Reverse Bits in Elements
1048+
case RISCV::VBREV_V:
1049+
// Vector Count Leading Zeros
1050+
case RISCV::VCLZ_V:
1051+
// Vector Count Trailing Zeros
1052+
case RISCV::VCTZ_V:
1053+
// Vector Population Count
1054+
case RISCV::VCPOP_V:
1055+
// Vector Rotate Left
1056+
case RISCV::VROL_VV:
1057+
case RISCV::VROL_VX:
1058+
// Vector Rotate Right
1059+
case RISCV::VROR_VI:
1060+
case RISCV::VROR_VV:
1061+
case RISCV::VROR_VX:
1062+
// Vector Widening Shift Left Logical
10251063
case RISCV::VWSLL_VI:
10261064
case RISCV::VWSLL_VX:
10271065
case RISCV::VWSLL_VV:
1028-
10291066
// Vector Mask Instructions
10301067
// Vector Mask-Register Logical Instructions
10311068
// vmsbf.m set-before-first mask bit

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll‎

Lines changed: 11 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -3402,9 +3402,8 @@ define <vscale x 4 x double> @vfrec7(<vscale x 4 x float> %a) {
34023402
define <vscale x 4 x i32> @vandn_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
34033403
; CHECK-LABEL: vandn_vv:
34043404
; CHECK: # %bb.0:
3405-
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3406-
; CHECK-NEXT: vandn.vv v10, v8, v10
34073405
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3406+
; CHECK-NEXT: vandn.vv v10, v8, v10
34083407
; CHECK-NEXT: vadd.vv v8, v10, v8
34093408
; CHECK-NEXT: ret
34103409
%1 = call <vscale x 4 x i32> @llvm.riscv.vandn.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
@@ -3415,9 +3414,8 @@ define <vscale x 4 x i32> @vandn_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b
34153414
define <vscale x 4 x i32> @vandn_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {
34163415
; CHECK-LABEL: vandn_vx:
34173416
; CHECK: # %bb.0:
3418-
; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma
3419-
; CHECK-NEXT: vandn.vx v10, v8, a0
34203417
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
3418+
; CHECK-NEXT: vandn.vx v10, v8, a0
34213419
; CHECK-NEXT: vadd.vv v8, v10, v8
34223420
; CHECK-NEXT: ret
34233421
%1 = call <vscale x 4 x i32> @llvm.riscv.vandn.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)
@@ -3428,9 +3426,8 @@ define <vscale x 4 x i32> @vandn_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {
34283426
define <vscale x 4 x i32> @vbrev_v(<vscale x 4 x i32> %a, iXLen %vl) {
34293427
; CHECK-LABEL: vbrev_v:
34303428
; CHECK: # %bb.0:
3431-
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3432-
; CHECK-NEXT: vbrev.v v10, v8
34333429
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3430+
; CHECK-NEXT: vbrev.v v10, v8
34343431
; CHECK-NEXT: vadd.vv v8, v10, v8
34353432
; CHECK-NEXT: ret
34363433
%1 = call <vscale x 4 x i32> @llvm.riscv.vbrev.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)
@@ -3441,9 +3438,8 @@ define <vscale x 4 x i32> @vbrev_v(<vscale x 4 x i32> %a, iXLen %vl) {
34413438
define <vscale x 4 x i32> @vclz_v(<vscale x 4 x i32> %a, iXLen %vl) {
34423439
; CHECK-LABEL: vclz_v:
34433440
; CHECK: # %bb.0:
3444-
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3445-
; CHECK-NEXT: vclz.v v10, v8
34463441
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3442+
; CHECK-NEXT: vclz.v v10, v8
34473443
; CHECK-NEXT: vadd.vv v8, v10, v8
34483444
; CHECK-NEXT: ret
34493445
%1 = call <vscale x 4 x i32> @llvm.riscv.vclz.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)
@@ -3454,9 +3450,8 @@ define <vscale x 4 x i32> @vclz_v(<vscale x 4 x i32> %a, iXLen %vl) {
34543450
define <vscale x 4 x i32> @vcpop_v(<vscale x 4 x i32> %a, iXLen %vl) {
34553451
; CHECK-LABEL: vcpop_v:
34563452
; CHECK: # %bb.0:
3457-
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3458-
; CHECK-NEXT: vcpop.v v10, v8
34593453
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3454+
; CHECK-NEXT: vcpop.v v10, v8
34603455
; CHECK-NEXT: vadd.vv v8, v10, v8
34613456
; CHECK-NEXT: ret
34623457
%1 = call <vscale x 4 x i32> @llvm.riscv.vcpopv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)
@@ -3467,9 +3462,8 @@ define <vscale x 4 x i32> @vcpop_v(<vscale x 4 x i32> %a, iXLen %vl) {
34673462
define <vscale x 4 x i32> @vctz_v(<vscale x 4 x i32> %a, iXLen %vl) {
34683463
; CHECK-LABEL: vctz_v:
34693464
; CHECK: # %bb.0:
3470-
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3471-
; CHECK-NEXT: vctz.v v10, v8
34723465
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3466+
; CHECK-NEXT: vctz.v v10, v8
34733467
; CHECK-NEXT: vadd.vv v8, v10, v8
34743468
; CHECK-NEXT: ret
34753469
%1 = call <vscale x 4 x i32> @llvm.riscv.vctz.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)
@@ -3480,9 +3474,8 @@ define <vscale x 4 x i32> @vctz_v(<vscale x 4 x i32> %a, iXLen %vl) {
34803474
define <vscale x 4 x i32> @vror_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
34813475
; CHECK-LABEL: vror_vv:
34823476
; CHECK: # %bb.0:
3483-
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3484-
; CHECK-NEXT: vror.vv v10, v8, v10
34853477
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3478+
; CHECK-NEXT: vror.vv v10, v8, v10
34863479
; CHECK-NEXT: vadd.vv v8, v10, v8
34873480
; CHECK-NEXT: ret
34883481
%1 = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
@@ -3493,9 +3486,8 @@ define <vscale x 4 x i32> @vror_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b,
34933486
define <vscale x 4 x i32> @vror_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {
34943487
; CHECK-LABEL: vror_vx:
34953488
; CHECK: # %bb.0:
3496-
; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma
3497-
; CHECK-NEXT: vror.vx v10, v8, a0
34983489
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
3490+
; CHECK-NEXT: vror.vx v10, v8, a0
34993491
; CHECK-NEXT: vadd.vv v8, v10, v8
35003492
; CHECK-NEXT: ret
35013493
%1 = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)
@@ -3506,9 +3498,8 @@ define <vscale x 4 x i32> @vror_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {
35063498
define <vscale x 4 x i32> @vror_vi(<vscale x 4 x i32> %a, iXLen %vl) {
35073499
; CHECK-LABEL: vror_vi:
35083500
; CHECK: # %bb.0:
3509-
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3510-
; CHECK-NEXT: vror.vi v10, v8, 5
35113501
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3502+
; CHECK-NEXT: vror.vi v10, v8, 5
35123503
; CHECK-NEXT: vadd.vv v8, v10, v8
35133504
; CHECK-NEXT: ret
35143505
%1 = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen -1)
@@ -3519,9 +3510,8 @@ define <vscale x 4 x i32> @vror_vi(<vscale x 4 x i32> %a, iXLen %vl) {
35193510
define <vscale x 4 x i32> @vrol_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
35203511
; CHECK-LABEL: vrol_vv:
35213512
; CHECK: # %bb.0:
3522-
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3523-
; CHECK-NEXT: vrol.vv v10, v8, v10
35243513
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3514+
; CHECK-NEXT: vrol.vv v10, v8, v10
35253515
; CHECK-NEXT: vadd.vv v8, v10, v8
35263516
; CHECK-NEXT: ret
35273517
%1 = call <vscale x 4 x i32> @llvm.riscv.vrol.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
@@ -3532,9 +3522,8 @@ define <vscale x 4 x i32> @vrol_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b,
35323522
define <vscale x 4 x i32> @vrol_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {
35333523
; CHECK-LABEL: vrol_vx:
35343524
; CHECK: # %bb.0:
3535-
; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma
3536-
; CHECK-NEXT: vrol.vx v10, v8, a0
35373525
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
3526+
; CHECK-NEXT: vrol.vx v10, v8, a0
35383527
; CHECK-NEXT: vadd.vv v8, v10, v8
35393528
; CHECK-NEXT: ret
35403529
%1 = call <vscale x 4 x i32> @llvm.riscv.vrol.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)

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