[RISCV] Fix a crash in RISCVGatherScatterLowering

We were assuming that the constant must always be fixed length when this is not required.  Such code is unlikely after optimization, which is why we didn't see this previously.

Author: preames

llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp

@@ -107,6 +107,9 @@ bool RISCVGatherScatterLowering::isLegalTypeAndAlignment(Type *DataType,
 
 // TODO: Should we consider the mask when looking for a stride?
 static std::pair<Value *, Value *> matchStridedConstant(Constant *StartC) {
+  if (!isa<FixedVectorType>(StartC->getType()))
+    return std::make_pair(nullptr, nullptr);
+
   unsigned NumElts = cast<FixedVectorType>(StartC->getType())->getNumElements();
 
   // Check that the start value is a strided constant.

llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll

@@ -135,6 +135,23 @@ define void @scatter_loopless(<vscale x 1 x i64> %x, ptr %p, i64 %stride) {
   ret void
 }
 
+; We previously crashed expecting a constant to be fixed length.
+define void @constant_stride(<vscale x 1 x i64> %x, ptr %p, i64 %stride) {
+; CHECK-LABEL: @constant_stride(
+; CHECK-NEXT:    [[PTRS:%.*]] = getelementptr i32, ptr [[P:%.*]], <vscale x 1 x i64> zeroinitializer
+; CHECK-NEXT:    call void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64> [[X:%.*]], <vscale x 1 x ptr> [[PTRS]], i32 8, <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer))
+; CHECK-NEXT:    ret void
+;
+  %ptrs = getelementptr i32, ptr %p, <vscale x 1 x i64> zeroinitializer
+  call void @llvm.masked.scatter.nxv1i64.nxv1p0(
+  <vscale x 1 x i64> %x,
+  <vscale x 1 x ptr> %ptrs,
+  i32 8,
+  <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 1, i64 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer)
+  )
+  ret void
+}
+
 declare i64 @llvm.vscale.i64()
 declare void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64>, <vscale x 1 x ptr>, i32, <vscale x 1 x i1>)
 declare <vscale x 1 x i64> @llvm.masked.gather.nxv1i64.nxv1p0(<vscale x 1 x ptr>, i32, <vscale x 1 x i1>, <vscale x 1 x i64>)