|
| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s |
| 3 | +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s |
| 4 | +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s |
| 5 | +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s |
| 6 | + |
| 7 | +define i32 @fneg_select_i32(i32 %cond, i32 %a, i32 %b) { |
| 8 | + %neg.a = xor i32 %a, u0x80000000 |
| 9 | + %cmp = icmp eq i32 %cond, zeroinitializer |
| 10 | + %select = select i1 %cmp, i32 %neg.a, i32 %b |
| 11 | + ret i32 %select |
| 12 | +} |
| 13 | + |
| 14 | +define <2 x i32> @fneg_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) { |
| 15 | + %neg.a = xor <2 x i32> %a, splat (i32 u0x80000000) |
| 16 | + %cmp = icmp eq <2 x i32> %cond, zeroinitializer |
| 17 | + %select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b |
| 18 | + ret <2 x i32> %select |
| 19 | +} |
| 20 | + |
| 21 | +define i32 @fabs_select_i32(i32 %cond, i32 %a, i32 %b) { |
| 22 | + %neg.a = and i32 %a, u0x7fffffff |
| 23 | + %cmp = icmp eq i32 %cond, zeroinitializer |
| 24 | + %select = select i1 %cmp, i32 %neg.a, i32 %b |
| 25 | + ret i32 %select |
| 26 | +} |
| 27 | + |
| 28 | +define <2 x i32> @fabs_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) { |
| 29 | + %neg.a = and <2 x i32> %a, splat (i32 u0x7fffffff) |
| 30 | + %cmp = icmp eq <2 x i32> %cond, zeroinitializer |
| 31 | + %select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b |
| 32 | + ret <2 x i32> %select |
| 33 | +} |
| 34 | + |
| 35 | +define i32 @fneg_fabs_select_i32(i32 %cond, i32 %a, i32 %b) { |
| 36 | + %neg.a = or i32 %a, u0x80000000 |
| 37 | + %cmp = icmp eq i32 %cond, zeroinitializer |
| 38 | + %select = select i1 %cmp, i32 %neg.a, i32 %b |
| 39 | + ret i32 %select |
| 40 | +} |
| 41 | + |
| 42 | +define <2 x i32> @fneg_fabs_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) { |
| 43 | + %neg.a = or <2 x i32> %a, splat (i32 u0x80000000) |
| 44 | + %cmp = icmp eq <2 x i32> %cond, zeroinitializer |
| 45 | + %select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b |
| 46 | + ret <2 x i32> %select |
| 47 | +} |
| 48 | + |
| 49 | +define i64 @fneg_select_i64(i64 %cond, i64 %a, i64 %b) { |
| 50 | + %neg.a = xor i64 %a, u0x8000000000000000 |
| 51 | + %cmp = icmp eq i64 %cond, zeroinitializer |
| 52 | + %select = select i1 %cmp, i64 %neg.a, i64 %b |
| 53 | + ret i64 %select |
| 54 | +} |
| 55 | + |
| 56 | +define i64 @fabs_select_i64(i64 %cond, i64 %a, i64 %b) { |
| 57 | + %neg.a = and i64 %a, u0x7fffffffffffffff |
| 58 | + %cmp = icmp eq i64 %cond, zeroinitializer |
| 59 | + %select = select i1 %cmp, i64 %neg.a, i64 %b |
| 60 | + ret i64 %select |
| 61 | +} |
| 62 | + |
| 63 | +define i64 @fneg_fabs_select_i64(i64 %cond, i64 %a, i64 %b) { |
| 64 | + %neg.a = or i64 %a, u0x8000000000000000 |
| 65 | + %cmp = icmp eq i64 %cond, zeroinitializer |
| 66 | + %select = select i1 %cmp, i64 %neg.a, i64 %b |
| 67 | + ret i64 %select |
| 68 | +} |
0 commit comments