Use flag NE instead of MI

Author: rez5427

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -11631,9 +11631,9 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(
     }
 
     // Check for sign bit test patterns that can use TST optimization.
-    // (SELECT_CC setlt, singn_extend_inreg, 0, tval, fval)
+    // (SELECT_CC setlt, sign_extend_inreg, 0, tval, fval)
     //                          -> TST %operand, sign_bit; CSEL
-    // (SELECT_CC setlt, singn_extend, 0, tval, fval)
+    // (SELECT_CC setlt, sign_extend, 0, tval, fval)
     //                          -> TST %operand, sign_bit; CSEL
     if (CC == ISD::SETLT && RHSC && RHSC->isZero() && LHS.hasOneUse() &&
         (LHS.getOpcode() == ISD::SIGN_EXTEND_INREG ||
@@ -11667,7 +11667,7 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(
 
         SDValue Flags = TST.getValue(1);
         return DAG.getNode(AArch64ISD::CSEL, DL, TVal.getValueType(), TVal,
-                           FVal, DAG.getConstant(AArch64CC::MI, DL, MVT::i32),
+                           FVal, DAG.getConstant(AArch64CC::NE, DL, MVT::i32),
                            Flags);
       }
     }

llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll

@@ -79,7 +79,7 @@ define i32 @g_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: g_i8_sign_extend_inreg:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    tst w0, #0x80
-; CHECK-NEXT:    csel w8, w1, w2, mi
+; CHECK-NEXT:    csel w8, w1, w2, ne
 ; CHECK-NEXT:    add w0, w8, w0, uxtb
 ; CHECK-NEXT:    ret
 entry:
@@ -100,7 +100,7 @@ define i32 @g_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: g_i16_sign_extend_inreg:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    tst w0, #0x8000
-; CHECK-NEXT:    csel w8, w1, w2, mi
+; CHECK-NEXT:    csel w8, w1, w2, ne
 ; CHECK-NEXT:    add w0, w8, w0, uxth
 ; CHECK-NEXT:    ret
 entry:
@@ -166,7 +166,7 @@ define i64 @g_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: g_i32_sign_extend_i64:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    tst w0, #0x80000000
-; CHECK-NEXT:    csel x8, x1, x2, mi
+; CHECK-NEXT:    csel x8, x1, x2, ne
 ; CHECK-NEXT:    add x0, x8, w0, uxtw
 ; CHECK-NEXT:    ret
 entry:

llvm/test/CodeGen/AArch64/icmp.ll

@@ -2105,7 +2105,7 @@ define i32 @i8_signbit_tst_constants(i8 %x, i8 %y) {
 ; CHECK-SD-NEXT:    mov w8, #42 // =0x2a
 ; CHECK-SD-NEXT:    tst w9, #0x80
 ; CHECK-SD-NEXT:    mov w9, #20894 // =0x519e
-; CHECK-SD-NEXT:    csel w0, w9, w8, mi
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
 ; CHECK-SD-NEXT:    ret
 ;
 ; CHECK-GI-LABEL: i8_signbit_tst_constants:
@@ -2129,7 +2129,7 @@ define i32 @i8_signbit_variables(i8 %x, i8 %y, i32 %a, i32 %b) {
 ; CHECK-SD:       // %bb.0:
 ; CHECK-SD-NEXT:    add w8, w0, w1
 ; CHECK-SD-NEXT:    tst w8, #0x80
-; CHECK-SD-NEXT:    csel w0, w2, w3, mi
+; CHECK-SD-NEXT:    csel w0, w2, w3, ne
 ; CHECK-SD-NEXT:    ret
 ;
 ; CHECK-GI-LABEL: i8_signbit_variables:

llvm/test/CodeGen/AArch64/vecreduce-bool.ll

@@ -28,7 +28,7 @@ define i32 @reduce_and_v1i8(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    umov w8, v0.b[0]
 ; CHECK-NEXT:    tst w8, #0x80
-; CHECK-NEXT:    csel w0, w0, w1, mi
+; CHECK-NEXT:    csel w0, w0, w1, ne
 ; CHECK-NEXT:    ret
   %x = icmp slt <1 x i8> %a0, zeroinitializer
   %y = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %x)
@@ -122,7 +122,7 @@ define i32 @reduce_and_v1i16(<1 x i16> %a0, i32 %a1, i32 %a2) nounwind {
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    umov w8, v0.h[0]
 ; CHECK-NEXT:    tst w8, #0x8000
-; CHECK-NEXT:    csel w0, w0, w1, mi
+; CHECK-NEXT:    csel w0, w0, w1, ne
 ; CHECK-NEXT:    ret
   %x = icmp slt <1 x i16> %a0, zeroinitializer
   %y = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %x)
@@ -307,7 +307,7 @@ define i32 @reduce_or_v1i8(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    umov w8, v0.b[0]
 ; CHECK-NEXT:    tst w8, #0x80
-; CHECK-NEXT:    csel w0, w0, w1, mi
+; CHECK-NEXT:    csel w0, w0, w1, ne
 ; CHECK-NEXT:    ret
   %x = icmp slt <1 x i8> %a0, zeroinitializer
   %y = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %x)
@@ -401,7 +401,7 @@ define i32 @reduce_or_v1i16(<1 x i16> %a0, i32 %a1, i32 %a2) nounwind {
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    umov w8, v0.h[0]
 ; CHECK-NEXT:    tst w8, #0x8000
-; CHECK-NEXT:    csel w0, w0, w1, mi
+; CHECK-NEXT:    csel w0, w0, w1, ne
 ; CHECK-NEXT:    ret
   %x = icmp slt <1 x i16> %a0, zeroinitializer
   %y = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %x)
@@ -586,7 +586,7 @@ define i32 @reduce_xor_v1i8(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    umov w8, v0.b[0]
 ; CHECK-NEXT:    tst w8, #0x80
-; CHECK-NEXT:    csel w0, w0, w1, mi
+; CHECK-NEXT:    csel w0, w0, w1, ne
 ; CHECK-NEXT:    ret
   %x = icmp slt <1 x i8> %a0, zeroinitializer
   %y = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %x)
@@ -681,7 +681,7 @@ define i32 @reduce_xor_v1i16(<1 x i16> %a0, i32 %a1, i32 %a2) nounwind {
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    umov w8, v0.h[0]
 ; CHECK-NEXT:    tst w8, #0x8000
-; CHECK-NEXT:    csel w0, w0, w1, mi
+; CHECK-NEXT:    csel w0, w0, w1, ne
 ; CHECK-NEXT:    ret
   %x = icmp slt <1 x i16> %a0, zeroinitializer
   %y = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %x)