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ArielCPUArielCPU
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Merge branch 'main' into users/arielcpu/mips-i6400-i6500-fix
2 parents 6c39322 + ab71b77 commit d53174d

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11 files changed

+271
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‎.github/workflows/build-ci-container-tooling.yml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ jobs:
7272
- name: Test Container
7373
run: |
7474
# Use --pull=never to ensure we are testing the just built image.
75-
podman run --pull=never --rm -it ${{ steps.vars.outputs.container-name-format-tag }} /usr/bin/bash -x -c 'cd $HOME && clang-format --version | grep version && black --version | grep black'
75+
podman run --pull=never --rm -it ${{ steps.vars.outputs.container-name-format-tag }} /usr/bin/bash -x -c 'cd $HOME && clang-format --version | grep version && git-clang-format -h | grep usage && black --version | grep black'
7676
podman run --pull=never --rm -it ${{ steps.vars.outputs.container-name-lint-tag }} /usr/bin/bash -x -c 'cd $HOME && clang-tidy --version | grep version && clang-tidy-diff.py -h | grep usage'
7777
7878
push-ci-container:

‎.github/workflows/containers/github-action-ci-tooling/Dockerfile‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,8 @@ RUN apt-get update && \
1010
tar -xvJf llvm.tar.xz -C /llvm-extract \
1111
# Only unpack these tools to save space on Github runner.
1212
LLVM-${LLVM_VERSION}-Linux-X64/bin/clang-tidy \
13-
LLVM-${LLVM_VERSION}-Linux-X64/bin/clang-format && \
13+
LLVM-${LLVM_VERSION}-Linux-X64/bin/clang-format \
14+
LLVM-${LLVM_VERSION}-Linux-X64/bin/git-clang-format && \
1415
rm llvm.tar.xz
1516

1617

@@ -35,7 +36,9 @@ RUN apt-get update && \
3536
FROM base AS ci-container-code-format
3637
ARG LLVM_VERSION
3738

38-
COPY --from=llvm-downloader /llvm-extract/LLVM-${LLVM_VERSION}-Linux-X64/bin/clang-format ${LLVM_SYSROOT}/bin/clang-format
39+
COPY --from=llvm-downloader /llvm-extract/LLVM-${LLVM_VERSION}-Linux-X64/bin/clang-format \
40+
/llvm-extract/LLVM-${LLVM_VERSION}-Linux-X64/bin/git-clang-format \
41+
${LLVM_SYSROOT}/bin/
3942

4043
ENV PATH=${LLVM_SYSROOT}/bin:${PATH}
4144

‎clang/include/clang/Driver/Distro.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,7 @@ class Distro {
7979
UbuntuOracular,
8080
UbuntuPlucky,
8181
UbuntuQuesting,
82+
UbuntuResolute,
8283
UnknownDistro
8384
};
8485

@@ -130,7 +131,7 @@ class Distro {
130131
}
131132

132133
bool IsUbuntu() const {
133-
return DistroVal >= UbuntuMaverick && DistroVal <= UbuntuQuesting;
134+
return DistroVal >= UbuntuMaverick && DistroVal <= UbuntuResolute;
134135
}
135136

136137
bool IsAlpineLinux() const { return DistroVal == AlpineLinux; }

‎clang/lib/AST/ByteCode/InterpBuiltin.cpp‎

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -1633,8 +1633,8 @@ static bool interp__builtin_elementwise_countzeroes(InterpState &S,
16331633
const InterpFrame *Frame,
16341634
const CallExpr *Call,
16351635
unsigned BuiltinID) {
1636-
const bool HasZeroArg = Call->getNumArgs() == 2;
1637-
const bool IsCTTZ = BuiltinID == Builtin::BI__builtin_elementwise_ctzg;
1636+
bool HasZeroArg = Call->getNumArgs() == 2;
1637+
bool IsCTTZ = BuiltinID == Builtin::BI__builtin_elementwise_ctzg;
16381638
assert(Call->getNumArgs() == 1 || HasZeroArg);
16391639
if (Call->getArg(0)->getType()->isIntegerType()) {
16401640
PrimType ArgT = *S.getContext().classify(Call->getArg(0)->getType());
@@ -2447,18 +2447,18 @@ interp__builtin_x86_pack(InterpState &S, CodePtr, const CallExpr *E,
24472447
const Pointer &Dst = S.Stk.peek<Pointer>();
24482448

24492449
const ASTContext &ASTCtx = S.getASTContext();
2450-
const unsigned SrcBits = ASTCtx.getIntWidth(VT0->getElementType());
2451-
const unsigned LHSVecLen = VT0->getNumElements();
2452-
const unsigned SrcPerLane = 128 / SrcBits;
2453-
const unsigned Lanes = LHSVecLen * SrcBits / 128;
2450+
unsigned SrcBits = ASTCtx.getIntWidth(VT0->getElementType());
2451+
unsigned LHSVecLen = VT0->getNumElements();
2452+
unsigned SrcPerLane = 128 / SrcBits;
2453+
unsigned Lanes = LHSVecLen * SrcBits / 128;
24542454

24552455
PrimType SrcT = *S.getContext().classify(VT0->getElementType());
24562456
PrimType DstT = *S.getContext().classify(getElemType(Dst));
2457-
const bool IsUnsigend = getElemType(Dst)->isUnsignedIntegerType();
2457+
bool IsUnsigend = getElemType(Dst)->isUnsignedIntegerType();
24582458

24592459
for (unsigned Lane = 0; Lane != Lanes; ++Lane) {
2460-
const unsigned BaseSrc = Lane * SrcPerLane;
2461-
const unsigned BaseDst = Lane * (2 * SrcPerLane);
2460+
unsigned BaseSrc = Lane * SrcPerLane;
2461+
unsigned BaseDst = Lane * (2 * SrcPerLane);
24622462

24632463
for (unsigned I = 0; I != SrcPerLane; ++I) {
24642464
INT_TYPE_SWITCH_NO_BOOL(SrcT, {
@@ -2596,9 +2596,9 @@ static bool interp__builtin_elementwise_triop_fp(
25962596

25972597
FPOptions FPO = Call->getFPFeaturesInEffect(S.Ctx.getLangOpts());
25982598
llvm::RoundingMode RM = getRoundingMode(FPO);
2599-
const QualType Arg1Type = Call->getArg(0)->getType();
2600-
const QualType Arg2Type = Call->getArg(1)->getType();
2601-
const QualType Arg3Type = Call->getArg(2)->getType();
2599+
QualType Arg1Type = Call->getArg(0)->getType();
2600+
QualType Arg2Type = Call->getArg(1)->getType();
2601+
QualType Arg3Type = Call->getArg(2)->getType();
26022602

26032603
// Non-vector floating point types.
26042604
if (!Arg1Type->isVectorType()) {
@@ -2621,16 +2621,16 @@ static bool interp__builtin_elementwise_triop_fp(
26212621
assert(Arg1Type->isVectorType() && Arg2Type->isVectorType() &&
26222622
Arg3Type->isVectorType());
26232623

2624-
const VectorType *VecT = Arg1Type->castAs<VectorType>();
2625-
const QualType ElemT = VecT->getElementType();
2626-
unsigned NumElems = VecT->getNumElements();
2624+
const VectorType *VecTy = Arg1Type->castAs<VectorType>();
2625+
QualType ElemQT = VecTy->getElementType();
2626+
unsigned NumElems = VecTy->getNumElements();
26272627

2628-
assert(ElemT == Arg2Type->castAs<VectorType>()->getElementType() &&
2629-
ElemT == Arg3Type->castAs<VectorType>()->getElementType());
2628+
assert(ElemQT == Arg2Type->castAs<VectorType>()->getElementType() &&
2629+
ElemQT == Arg3Type->castAs<VectorType>()->getElementType());
26302630
assert(NumElems == Arg2Type->castAs<VectorType>()->getNumElements() &&
26312631
NumElems == Arg3Type->castAs<VectorType>()->getNumElements());
2632-
assert(ElemT->isRealFloatingType());
2633-
(void)ElemT;
2632+
assert(ElemQT->isRealFloatingType());
2633+
(void)ElemQT;
26342634

26352635
const Pointer &VZ = S.Stk.pop<Pointer>();
26362636
const Pointer &VY = S.Stk.pop<Pointer>();
@@ -2775,7 +2775,7 @@ static bool interp__builtin_elementwise_triop(
27752775
}
27762776

27772777
const auto *VecT = Arg0Type->castAs<VectorType>();
2778-
const PrimType &ElemT = *S.getContext().classify(VecT->getElementType());
2778+
PrimType ElemT = *S.getContext().classify(VecT->getElementType());
27792779
unsigned NumElems = VecT->getNumElements();
27802780
bool DestUnsigned = Call->getType()->isUnsignedIntegerOrEnumerationType();
27812781

@@ -2847,9 +2847,9 @@ static bool interp__builtin_x86_insert_subvector(InterpState &S, CodePtr OpPC,
28472847
unsigned Lane = static_cast<unsigned>(Index % NumLanes);
28482848
unsigned InsertPos = Lane * SubElements;
28492849

2850-
PrimType ElemPT = BaseVec.getFieldDesc()->getPrimType();
2850+
PrimType ElemT = BaseVec.getFieldDesc()->getPrimType();
28512851

2852-
TYPE_SWITCH(ElemPT, {
2852+
TYPE_SWITCH(ElemT, {
28532853
for (unsigned I = 0; I != BaseElements; ++I)
28542854
Dst.elem<T>(I) = BaseVec.elem<T>(I);
28552855
for (unsigned I = 0; I != SubElements; ++I)
@@ -2872,12 +2872,12 @@ static bool interp__builtin_ia32_pternlog(InterpState &S, CodePtr OpPC,
28722872
const Pointer &Dst = S.Stk.peek<Pointer>();
28732873

28742874
unsigned DstLen = A.getNumElems();
2875-
const QualType ElemQT = getElemType(A);
2876-
const OptPrimType ElemPT = S.getContext().classify(ElemQT);
2875+
QualType ElemQT = getElemType(A);
2876+
OptPrimType ElemT = S.getContext().classify(ElemQT);
28772877
unsigned LaneWidth = S.getASTContext().getTypeSize(ElemQT);
28782878
bool DstUnsigned = ElemQT->isUnsignedIntegerOrEnumerationType();
28792879

2880-
INT_TYPE_SWITCH_NO_BOOL(*ElemPT, {
2880+
INT_TYPE_SWITCH_NO_BOOL(*ElemT, {
28812881
for (unsigned I = 0; I != DstLen; ++I) {
28822882
APInt ALane = A.elem<T>(I).toAPSInt();
28832883
APInt BLane = B.elem<T>(I).toAPSInt();
@@ -2916,13 +2916,13 @@ static bool interp__builtin_vec_ext(InterpState &S, CodePtr OpPC,
29162916
unsigned Index =
29172917
static_cast<unsigned>(ImmAPS.getZExtValue() & (NumElems - 1));
29182918

2919-
PrimType ElemPT = Vec.getFieldDesc()->getPrimType();
2919+
PrimType ElemT = Vec.getFieldDesc()->getPrimType();
29202920
// FIXME(#161685): Replace float+int split with a numeric-only type switch
2921-
if (ElemPT == PT_Float) {
2921+
if (ElemT == PT_Float) {
29222922
S.Stk.push<Floating>(Vec.elem<Floating>(Index));
29232923
return true;
29242924
}
2925-
INT_TYPE_SWITCH_NO_BOOL(ElemPT, {
2925+
INT_TYPE_SWITCH_NO_BOOL(ElemT, {
29262926
APSInt V = Vec.elem<T>(Index).toAPSInt();
29272927
pushInteger(S, V, Call->getType());
29282928
});
@@ -2947,8 +2947,8 @@ static bool interp__builtin_vec_set(InterpState &S, CodePtr OpPC,
29472947
unsigned Index =
29482948
static_cast<unsigned>(ImmAPS.getZExtValue() & (NumElems - 1));
29492949

2950-
PrimType ElemPT = Base.getFieldDesc()->getPrimType();
2951-
INT_TYPE_SWITCH_NO_BOOL(ElemPT, {
2950+
PrimType ElemT = Base.getFieldDesc()->getPrimType();
2951+
INT_TYPE_SWITCH_NO_BOOL(ElemT, {
29522952
for (unsigned I = 0; I != NumElems; ++I)
29532953
Dst.elem<T>(I) = Base.elem<T>(I);
29542954
Dst.elem<T>(Index) = static_cast<T>(ValAPS);

‎clang/lib/Driver/Distro.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,7 @@ static Distro::DistroType DetectLsbRelease(llvm::vfs::FileSystem &VFS) {
9292
.Case("oracular", Distro::UbuntuOracular)
9393
.Case("plucky", Distro::UbuntuPlucky)
9494
.Case("questing", Distro::UbuntuQuesting)
95+
.Case("resolute", Distro::UbuntuResolute)
9596
.Default(Distro::UnknownDistro);
9697
return Version;
9798
}

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19093,7 +19093,8 @@ static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) {
1909319093
SDValue Ext1 = Op1.getOperand(0);
1909419094
if (Ext0.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
1909519095
Ext1.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
19096-
Ext0.getOperand(0) != Ext1.getOperand(0))
19096+
Ext0.getOperand(0) != Ext1.getOperand(0) ||
19097+
Ext0.getOperand(0).getValueType().isScalableVector())
1909719098
return SDValue();
1909819099
// Check that the type is twice the add types, and the extract are from
1909919100
// upper/lower parts of the same source.

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