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[X86] x86-64-double-shifts-var.ll - regenerate with update_llc_test_checks script to show full codegen
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‎llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll‎

Lines changed: 84 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,22 +1,23 @@
1-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=k8 | FileCheck %s
2-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=opteron | FileCheck %s
3-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon64 | FileCheck %s
4-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-fx | FileCheck %s
5-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=k8-sse3 | FileCheck %s
6-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=opteron-sse3 | FileCheck %s
7-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon64-sse3 | FileCheck %s
8-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=amdfam10 | FileCheck %s
9-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver1 | FileCheck %s
10-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver2 | FileCheck %s
11-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver1 | FileCheck %s
12-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver3 | FileCheck %s
14-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s
15-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s
16-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s
17-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s
18-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s
19-
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=k8 | FileCheck %s --check-prefixes=X64
3+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=opteron | FileCheck %s --check-prefixes=X64
4+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon64 | FileCheck %s --check-prefixes=X64
5+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-fx | FileCheck %s --check-prefixes=X64
6+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=k8-sse3 | FileCheck %s --check-prefixes=X64
7+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=opteron-sse3 | FileCheck %s --check-prefixes=X64
8+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon64-sse3 | FileCheck %s --check-prefixes=X64
9+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=amdfam10 | FileCheck %s --check-prefixes=X64
10+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver1 | FileCheck %s --check-prefixes=X64
11+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver2 | FileCheck %s --check-prefixes=BMI
12+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver1 | FileCheck %s --check-prefixes=BMI
13+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s --check-prefixes=BMI
14+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver3 | FileCheck %s --check-prefixes=BMI
15+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s --check-prefixes=BMI2
16+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s --check-prefixes=BMI2
17+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefixes=BMI2
18+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=BMI2
19+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=BMI2
20+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=BMI2
2021

2122
; Verify that for the X86_64 processors that are known to have poor latency
2223
; double precision shift instructions we do not generate 'shld' or 'shrd'
@@ -28,8 +29,40 @@
2829
;}
2930

3031
define i64 @lshift(i64 %a, i64 %b, i32 %c) nounwind readnone {
32+
; X64-LABEL: lshift:
33+
; X64: # %bb.0: # %entry
34+
; X64-NEXT: movl %edx, %ecx
35+
; X64-NEXT: movq %rsi, %rax
36+
; X64-NEXT: shlq %cl, %rdi
37+
; X64-NEXT: shrq %rax
38+
; X64-NEXT: notb %cl
39+
; X64-NEXT: # kill: def $cl killed $cl killed $ecx
40+
; X64-NEXT: shrq %cl, %rax
41+
; X64-NEXT: orq %rdi, %rax
42+
; X64-NEXT: retq
43+
;
44+
; BMI-LABEL: lshift:
45+
; BMI: # %bb.0: # %entry
46+
; BMI-NEXT: movq %rsi, %rax
47+
; BMI-NEXT: movl %edx, %ecx
48+
; BMI-NEXT: shrq %rax
49+
; BMI-NEXT: shlq %cl, %rdi
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; BMI-NEXT: notb %cl
51+
; BMI-NEXT: # kill: def $cl killed $cl killed $ecx
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; BMI-NEXT: shrq %cl, %rax
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; BMI-NEXT: orq %rdi, %rax
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; BMI-NEXT: retq
55+
;
56+
; BMI2-LABEL: lshift:
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; BMI2: # %bb.0: # %entry
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; BMI2-NEXT: # kill: def $edx killed $edx def $rdx
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; BMI2-NEXT: shlxq %rdx, %rdi, %rcx
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; BMI2-NEXT: notb %dl
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; BMI2-NEXT: shrq %rsi
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; BMI2-NEXT: shrxq %rdx, %rsi, %rax
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; BMI2-NEXT: orq %rcx, %rax
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; BMI2-NEXT: retq
3165
entry:
32-
; CHECK-NOT: shld
3366
%sh_prom = zext i32 %c to i64
3467
%shl = shl i64 %a, %sh_prom
3568
%sub = sub nsw i32 64, %c
@@ -45,8 +78,38 @@ entry:
4578
;}
4679

4780
define i64 @rshift(i64 %a, i64 %b, i32 %c) nounwind readnone {
81+
; X64-LABEL: rshift:
82+
; X64: # %bb.0: # %entry
83+
; X64-NEXT: movl %edx, %ecx
84+
; X64-NEXT: shrq %cl, %rdi
85+
; X64-NEXT: leaq (%rsi,%rsi), %rax
86+
; X64-NEXT: notb %cl
87+
; X64-NEXT: # kill: def $cl killed $cl killed $ecx
88+
; X64-NEXT: shlq %cl, %rax
89+
; X64-NEXT: orq %rdi, %rax
90+
; X64-NEXT: retq
91+
;
92+
; BMI-LABEL: rshift:
93+
; BMI: # %bb.0: # %entry
94+
; BMI-NEXT: movl %edx, %ecx
95+
; BMI-NEXT: leaq (%rsi,%rsi), %rax
96+
; BMI-NEXT: shrq %cl, %rdi
97+
; BMI-NEXT: notb %cl
98+
; BMI-NEXT: # kill: def $cl killed $cl killed $ecx
99+
; BMI-NEXT: shlq %cl, %rax
100+
; BMI-NEXT: orq %rdi, %rax
101+
; BMI-NEXT: retq
102+
;
103+
; BMI2-LABEL: rshift:
104+
; BMI2: # %bb.0: # %entry
105+
; BMI2-NEXT: # kill: def $edx killed $edx def $rdx
106+
; BMI2-NEXT: shrxq %rdx, %rdi, %rcx
107+
; BMI2-NEXT: notb %dl
108+
; BMI2-NEXT: addq %rsi, %rsi
109+
; BMI2-NEXT: shlxq %rdx, %rsi, %rax
110+
; BMI2-NEXT: orq %rcx, %rax
111+
; BMI2-NEXT: retq
48112
entry:
49-
; CHECK-NOT: shrd
50113
%sh_prom = zext i32 %c to i64
51114
%shr = lshr i64 %a, %sh_prom
52115
%sub = sub nsw i32 64, %c

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