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VyacheslavLevytskyyVyacheslavLevytskyy
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fix generation of gMIR vs. SPIR-V
1 parent 059f044 commit d579bb2

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6 files changed

+46
-38
lines changed

6 files changed

+46
-38
lines changed

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp‎

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -476,8 +476,9 @@ static bool buildSelectInst(MachineIRBuilder &MIRBuilder,
476476
if (ReturnType->getOpcode() == SPIRV::OpTypeVector) {
477477
unsigned Bits = GR->getScalarOrVectorBitWidth(ReturnType);
478478
uint64_t AllOnes = APInt::getAllOnes(Bits).getZExtValue();
479-
TrueConst = GR->getOrCreateConsIntVector(AllOnes, MIRBuilder, ReturnType);
480-
FalseConst = GR->getOrCreateConsIntVector(0, MIRBuilder, ReturnType);
479+
TrueConst =
480+
GR->getOrCreateConsIntVector(AllOnes, MIRBuilder, ReturnType, true);
481+
FalseConst = GR->getOrCreateConsIntVector(0, MIRBuilder, ReturnType, true);
481482
} else {
482483
TrueConst = GR->buildConstantInt(1, MIRBuilder, ReturnType);
483484
FalseConst = GR->buildConstantInt(0, MIRBuilder, ReturnType);
@@ -1457,7 +1458,7 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call,
14571458
ToTruncate = DefaultReg;
14581459
}
14591460
auto NewRegister =
1460-
GR->buildConstantInt(DefaultValue, MIRBuilder, PointerSizeType);
1461+
GR->buildConstantInt(DefaultValue, MIRBuilder, PointerSizeType, true);
14611462
MIRBuilder.buildCopy(DefaultReg, NewRegister);
14621463
} else { // If it could be in range, we need to load from the given builtin.
14631464
auto Vec3Ty =
@@ -1492,13 +1493,14 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call,
14921493
GR->assignSPIRVTypeToVReg(BoolType, CompareRegister, MIRBuilder.getMF());
14931494

14941495
// Use G_ICMP to check if idxVReg < 3.
1495-
MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CompareRegister, IndexRegister,
1496-
GR->buildConstantInt(3, MIRBuilder, IndexType));
1496+
MIRBuilder.buildICmp(
1497+
CmpInst::ICMP_ULT, CompareRegister, IndexRegister,
1498+
GR->buildConstantInt(3, MIRBuilder, IndexType, true));
14971499

14981500
// Get constant for the default value (0 or 1 depending on which
14991501
// function).
15001502
Register DefaultRegister =
1501-
GR->buildConstantInt(DefaultValue, MIRBuilder, PointerSizeType);
1503+
GR->buildConstantInt(DefaultValue, MIRBuilder, PointerSizeType, true);
15021504

15031505
// Get a register for the selection result (possibly a new temporary one).
15041506
Register SelectionResult = Call->ReturnRegister;
@@ -2277,7 +2279,7 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call,
22772279
Const = GR->getOrCreateConstIntArray(0, Size, *MIRBuilder.getInsertPt(),
22782280
SpvFieldTy, *ST.getInstrInfo());
22792281
} else {
2280-
Const = GR->buildConstantInt(0, MIRBuilder, SpvTy);
2282+
Const = GR->buildConstantInt(0, MIRBuilder, SpvTy, true);
22812283
}
22822284
if (!LocalWorkSize.isValid())
22832285
LocalWorkSize = Const;

‎llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -669,7 +669,8 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
669669
// Make sure there's a valid return reg, even for functions returning void.
670670
if (!ResVReg.isValid())
671671
ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
672-
SPIRVType *RetType = GR->assignTypeToVReg(OrigRetTy, ResVReg, MIRBuilder);
672+
SPIRVType *RetType = GR->assignTypeToVReg(
673+
OrigRetTy, ResVReg, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, true);
673674

674675
// Emit the call instruction and its args.
675676
auto MIB = MIRBuilder.buildInstr(CallOp)

‎llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -193,7 +193,8 @@ bool SPIRVEmitNonSemanticDI::emitGlobalDI(MachineFunction &MF) {
193193
};
194194

195195
const SPIRVType *VoidTy =
196-
GR->getOrCreateSPIRVType(Type::getVoidTy(*Context), MIRBuilder);
196+
GR->getOrCreateSPIRVType(Type::getVoidTy(*Context), MIRBuilder,
197+
SPIRV::AccessQualifier::ReadWrite, false);
197198

198199
const auto EmitDIInstruction =
199200
[&](SPIRV::NonSemanticExtInst::NonSemanticExtInst Inst,
@@ -217,7 +218,8 @@ bool SPIRVEmitNonSemanticDI::emitGlobalDI(MachineFunction &MF) {
217218
};
218219

219220
const SPIRVType *I32Ty =
220-
GR->getOrCreateSPIRVType(Type::getInt32Ty(*Context), MIRBuilder);
221+
GR->getOrCreateSPIRVType(Type::getInt32Ty(*Context), MIRBuilder,
222+
SPIRV::AccessQualifier::ReadWrite, false);
221223

222224
const Register DwarfVersionReg =
223225
GR->buildConstantInt(DwarfVersion, MIRBuilder, I32Ty, false);

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp‎

Lines changed: 18 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,8 @@ SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType,
244244
CurMF->getRegInfo().createGenericVirtualRegister(LLT::scalar(BitWidth));
245245
CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
246246
if (MIRBuilder)
247-
assignTypeToVReg(LLVMIntTy, Res, *MIRBuilder);
247+
assignTypeToVReg(LLVMIntTy, Res, *MIRBuilder,
248+
SPIRV::AccessQualifier::ReadWrite, true);
248249
else
249250
assignIntTypeToVReg(BitWidth, Res, *I, *TII);
250251
DT.add(CI, CurMF, Res);
@@ -271,7 +272,8 @@ SPIRVGlobalRegistry::getOrCreateConstFloatReg(APFloat Val, SPIRVType *SpvType,
271272
CurMF->getRegInfo().createGenericVirtualRegister(LLT::scalar(BitWidth));
272273
CurMF->getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
273274
if (MIRBuilder)
274-
assignTypeToVReg(LLVMFloatTy, Res, *MIRBuilder);
275+
assignTypeToVReg(LLVMFloatTy, Res, *MIRBuilder,
276+
SPIRV::AccessQualifier::ReadWrite, true);
275277
else
276278
assignFloatTypeToVReg(BitWidth, Res, *I, *TII);
277279
DT.add(CI, CurMF, Res);
@@ -878,12 +880,13 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeOpaque(const StructType *Ty,
878880
});
879881
}
880882

881-
SPIRVType *SPIRVGlobalRegistry::getOpTypeStruct(const StructType *Ty,
882-
MachineIRBuilder &MIRBuilder,
883-
bool EmitIR) {
883+
SPIRVType *SPIRVGlobalRegistry::getOpTypeStruct(
884+
const StructType *Ty, MachineIRBuilder &MIRBuilder,
885+
SPIRV::AccessQualifier::AccessQualifier AccQual, bool EmitIR) {
884886
SmallVector<Register, 4> FieldTypes;
885887
for (const auto &Elem : Ty->elements()) {
886-
SPIRVType *ElemTy = findSPIRVType(toTypedPointer(Elem), MIRBuilder);
888+
SPIRVType *ElemTy =
889+
findSPIRVType(toTypedPointer(Elem), MIRBuilder, AccQual, EmitIR);
887890
assert(ElemTy && ElemTy->getOpcode() != SPIRV::OpTypeVoid &&
888891
"Invalid struct element type");
889892
FieldTypes.push_back(getSPIRVTypeID(ElemTy));
@@ -1017,26 +1020,27 @@ SPIRVType *SPIRVGlobalRegistry::createSPIRVType(
10171020
if (Ty->isVoidTy())
10181021
return getOpTypeVoid(MIRBuilder);
10191022
if (Ty->isVectorTy()) {
1020-
SPIRVType *El =
1021-
findSPIRVType(cast<FixedVectorType>(Ty)->getElementType(), MIRBuilder);
1023+
SPIRVType *El = findSPIRVType(cast<FixedVectorType>(Ty)->getElementType(),
1024+
MIRBuilder, AccQual, EmitIR);
10221025
return getOpTypeVector(cast<FixedVectorType>(Ty)->getNumElements(), El,
10231026
MIRBuilder);
10241027
}
10251028
if (Ty->isArrayTy()) {
1026-
SPIRVType *El = findSPIRVType(Ty->getArrayElementType(), MIRBuilder);
1029+
SPIRVType *El =
1030+
findSPIRVType(Ty->getArrayElementType(), MIRBuilder, AccQual, EmitIR);
10271031
return getOpTypeArray(Ty->getArrayNumElements(), El, MIRBuilder, EmitIR);
10281032
}
10291033
if (auto SType = dyn_cast<StructType>(Ty)) {
10301034
if (SType->isOpaque())
10311035
return getOpTypeOpaque(SType, MIRBuilder);
1032-
return getOpTypeStruct(SType, MIRBuilder, EmitIR);
1036+
return getOpTypeStruct(SType, MIRBuilder, AccQual, EmitIR);
10331037
}
10341038
if (auto FType = dyn_cast<FunctionType>(Ty)) {
1035-
SPIRVType *RetTy = findSPIRVType(FType->getReturnType(), MIRBuilder);
1039+
SPIRVType *RetTy =
1040+
findSPIRVType(FType->getReturnType(), MIRBuilder, AccQual, EmitIR);
10361041
SmallVector<SPIRVType *, 4> ParamTypes;
1037-
for (const auto &t : FType->params()) {
1038-
ParamTypes.push_back(findSPIRVType(t, MIRBuilder));
1039-
}
1042+
for (const auto &ParamTy : FType->params())
1043+
ParamTypes.push_back(findSPIRVType(ParamTy, MIRBuilder, AccQual, EmitIR));
10401044
return getOpTypeFunction(RetTy, ParamTypes, MIRBuilder);
10411045
}
10421046

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h‎

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -94,13 +94,11 @@ class SPIRVGlobalRegistry {
9494

9595
// Add a new OpTypeXXX instruction without checking for duplicates.
9696
SPIRVType *createSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder,
97-
SPIRV::AccessQualifier::AccessQualifier AQ =
98-
SPIRV::AccessQualifier::ReadWrite,
99-
bool EmitIR = true);
97+
SPIRV::AccessQualifier::AccessQualifier AQ,
98+
bool EmitIR);
10099
SPIRVType *findSPIRVType(const Type *Ty, MachineIRBuilder &MIRBuilder,
101-
SPIRV::AccessQualifier::AccessQualifier accessQual =
102-
SPIRV::AccessQualifier::ReadWrite,
103-
bool EmitIR = true);
100+
SPIRV::AccessQualifier::AccessQualifier accessQual,
101+
bool EmitIR);
104102
SPIRVType *
105103
restOfCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder,
106104
SPIRV::AccessQualifier::AccessQualifier AccessQual,
@@ -321,9 +319,8 @@ class SPIRVGlobalRegistry {
321319
// and map it to the given VReg by creating an ASSIGN_TYPE instruction.
322320
SPIRVType *assignTypeToVReg(const Type *Type, Register VReg,
323321
MachineIRBuilder &MIRBuilder,
324-
SPIRV::AccessQualifier::AccessQualifier AQ =
325-
SPIRV::AccessQualifier::ReadWrite,
326-
bool EmitIR = true);
322+
SPIRV::AccessQualifier::AccessQualifier AQ,
323+
bool EmitIR);
327324
SPIRVType *assignIntTypeToVReg(unsigned BitWidth, Register VReg,
328325
MachineInstr &I, const SPIRVInstrInfo &TII);
329326
SPIRVType *assignFloatTypeToVReg(unsigned BitWidth, Register VReg,
@@ -470,13 +467,14 @@ class SPIRVGlobalRegistry {
470467
MachineIRBuilder &MIRBuilder);
471468

472469
SPIRVType *getOpTypeArray(uint32_t NumElems, SPIRVType *ElemType,
473-
MachineIRBuilder &MIRBuilder, bool EmitIR = true);
470+
MachineIRBuilder &MIRBuilder, bool EmitIR);
474471

475472
SPIRVType *getOpTypeOpaque(const StructType *Ty,
476473
MachineIRBuilder &MIRBuilder);
477474

478475
SPIRVType *getOpTypeStruct(const StructType *Ty, MachineIRBuilder &MIRBuilder,
479-
bool EmitIR = true);
476+
SPIRV::AccessQualifier::AccessQualifier AccQual,
477+
bool EmitIR);
480478

481479
SPIRVType *getOpTypePointer(SPIRV::StorageClass::StorageClass SC,
482480
SPIRVType *ElemType, MachineIRBuilder &MIRBuilder,
@@ -539,7 +537,7 @@ class SPIRVGlobalRegistry {
539537
SPIRVType *SpvType,
540538
const SPIRVInstrInfo &TII);
541539
Register getOrCreateConsIntVector(uint64_t Val, MachineIRBuilder &MIRBuilder,
542-
SPIRVType *SpvType, bool EmitIR = true);
540+
SPIRVType *SpvType, bool EmitIR);
543541
Register getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder,
544542
SPIRVType *SpvType);
545543
Register buildConstantSampler(Register Res, unsigned AddrMode, unsigned Param,

‎llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -192,7 +192,7 @@ static void validateGroupWaitEventsPtr(const SPIRVSubtarget &STI,
192192
// Insert a bitcast before the instruction to keep SPIR-V code valid.
193193
LLVMContext &Context = MF->getFunction().getContext();
194194
SPIRVType *NewPtrType =
195-
createNewPtrType(GR, I, OpType, false, true, nullptr,
195+
createNewPtrType(GR, I, OpType, false, false, nullptr,
196196
TargetExtType::get(Context, "spirv.Event"));
197197
doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType);
198198
}
@@ -216,7 +216,8 @@ static void validateLifetimeStart(const SPIRVSubtarget &STI,
216216
MachineIRBuilder MIB(I);
217217
LLVMContext &Context = MF->getFunction().getContext();
218218
SPIRVType *ElemType =
219-
GR.getOrCreateSPIRVType(IntegerType::getInt8Ty(Context), MIB);
219+
GR.getOrCreateSPIRVType(IntegerType::getInt8Ty(Context), MIB,
220+
SPIRV::AccessQualifier::ReadWrite, false);
220221
SPIRVType *NewPtrType = GR.getOrCreateSPIRVPointerType(ElemType, MIB, SC);
221222
doInsertBitcast(STI, MRI, GR, I, PtrReg, 0, NewPtrType);
222223
}

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