@@ -1842,15 +1842,15 @@ def SVPMULLT_PAIR_N_U64 : SInst<"svpmullt_pair[_n_{d}]", "dda", "Ul", MergeNone,
18421842}
18431843
18441844let SVETargetGuard = "sve-aes2", SMETargetGuard = "sve-aes2,ssve-aes" in {
1845- def SVAESD_X2 : SInst<"svaesd_lane[_{d}_x2]", "22di", "Uc", MergeNone, "aarch64_sve_aesd_lane_x2", [IsOverloadNone, VerifyRuntimeMode]>;
1846- def SVAESDIMC_X2 : SInst<"svaesdimc_lane[_{d}_x2]", "22di", "Uc", MergeNone, "aarch64_sve_aesdimc_lane_x2", [IsOverloadNone, VerifyRuntimeMode]>;
1847- def SVAESE_X2 : SInst<"svaese_lane[_{d}_x2]", "22di", "Uc", MergeNone, "aarch64_sve_aese_lane_x2", [IsOverloadNone, VerifyRuntimeMode]>;
1848- def SVAESEMC_X2 : SInst<"svaesemc_lane[_{d}_x2]", "22di", "Uc", MergeNone, "aarch64_sve_aesemc_lane_x2", [IsOverloadNone, VerifyRuntimeMode]>;
1849-
1850- def SVAESD_X4 : SInst<"svaesd_lane[_{d}_x4]", "44di", "Uc", MergeNone, "aarch64_sve_aesd_lane_x4", [IsOverloadNone, VerifyRuntimeMode]>;
1851- def SVAESDIMC_X4 : SInst<"svaesdimc_lane[_{d}_x4]", "44di", "Uc", MergeNone, "aarch64_sve_aesdimc_lane_x4", [IsOverloadNone, VerifyRuntimeMode]>;
1852- def SVAESE_X4 : SInst<"svaese_lane[_{d}_x4]", "44di", "Uc", MergeNone, "aarch64_sve_aese_lane_x4", [IsOverloadNone, VerifyRuntimeMode]>;
1853- def SVAESEMC_X4 : SInst<"svaesemc_lane[_{d}_x4]", "44di", "Uc", MergeNone, "aarch64_sve_aesemc_lane_x4", [IsOverloadNone, VerifyRuntimeMode]>;
1845+ def SVAESD_X2 : SInst<"svaesd_lane[_{d}_x2]", "22di", "Uc", MergeNone, "aarch64_sve_aesd_lane_x2", [IsOverloadNone, VerifyRuntimeMode], [ImmCheck<2, ImmCheck0_3>] >;
1846+ def SVAESDIMC_X2 : SInst<"svaesdimc_lane[_{d}_x2]", "22di", "Uc", MergeNone, "aarch64_sve_aesdimc_lane_x2", [IsOverloadNone, VerifyRuntimeMode], [ImmCheck<2, ImmCheck0_3>] >;
1847+ def SVAESE_X2 : SInst<"svaese_lane[_{d}_x2]", "22di", "Uc", MergeNone, "aarch64_sve_aese_lane_x2", [IsOverloadNone, VerifyRuntimeMode], [ImmCheck<2, ImmCheck0_3>] >;
1848+ def SVAESEMC_X2 : SInst<"svaesemc_lane[_{d}_x2]", "22di", "Uc", MergeNone, "aarch64_sve_aesemc_lane_x2", [IsOverloadNone, VerifyRuntimeMode], [ImmCheck<2, ImmCheck0_3>] >;
1849+
1850+ def SVAESD_X4 : SInst<"svaesd_lane[_{d}_x4]", "44di", "Uc", MergeNone, "aarch64_sve_aesd_lane_x4", [IsOverloadNone, VerifyRuntimeMode], [ImmCheck<2, ImmCheck0_3>] >;
1851+ def SVAESDIMC_X4 : SInst<"svaesdimc_lane[_{d}_x4]", "44di", "Uc", MergeNone, "aarch64_sve_aesdimc_lane_x4", [IsOverloadNone, VerifyRuntimeMode], [ImmCheck<2, ImmCheck0_3>] >;
1852+ def SVAESE_X4 : SInst<"svaese_lane[_{d}_x4]", "44di", "Uc", MergeNone, "aarch64_sve_aese_lane_x4", [IsOverloadNone, VerifyRuntimeMode], [ImmCheck<2, ImmCheck0_3>] >;
1853+ def SVAESEMC_X4 : SInst<"svaesemc_lane[_{d}_x4]", "44di", "Uc", MergeNone, "aarch64_sve_aesemc_lane_x4", [IsOverloadNone, VerifyRuntimeMode], [ImmCheck<2, ImmCheck0_3>] >;
18541854
18551855def SVPMULL_PAIR_U64 : SInst<"svpmull_pair[_{d}_x2]", "2dd", "Ul", MergeNone, "aarch64_sve_pmull_pair_x2", [IsOverloadNone, VerifyRuntimeMode]>;
18561856def SVPMULL_PAIR_N_U64 : SInst<"svpmull_pair[_n_{d}_x2]", "2da", "Ul", MergeNone, "aarch64_sve_pmull_pair_x2", [IsOverloadNone, VerifyRuntimeMode]>;
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