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1 parent 7ffeaf0 commit d66084bCopy full SHA for d66084b
llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
@@ -1,7 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+experimental-zfbfmin,+experimental-zvfbfmin \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \
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; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
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-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+experimental-zfbfmin,+experimental-zvfbfmin \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \
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; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
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declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(
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