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--Added support for extension SPV_INTEL_arbitrary_precision_fixed_point
--Added test files for extension SPV_INTEL_arbitrary_precision_fixed_point
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7 files changed

+703
-2
lines changed

7 files changed

+703
-2
lines changed

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp‎

Lines changed: 75 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -697,7 +697,8 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call,
697697
MachineIRBuilder &MIRBuilder,
698698
SPIRVGlobalRegistry *GR) {
699699
if (Call->isSpirvOp())
700-
return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call, Register(0));
700+
return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call,
701+
Register(0));
701702

702703
Register ScopeRegister =
703704
buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
@@ -2282,6 +2283,77 @@ static bool generateBindlessImageINTELInst(const SPIRV::IncomingCall *Call,
22822283
return buildBindlessImageINTELInst(Call, Opcode, MIRBuilder, GR);
22832284
}
22842285

2286+
static bool buildAPFixedPointInst(const SPIRV::IncomingCall *Call,
2287+
unsigned Opcode, MachineIRBuilder &MIRBuilder,
2288+
SPIRVGlobalRegistry *GR) {
2289+
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
2290+
SmallVector<uint32_t, 1> ImmArgs;
2291+
Register InputReg = Call->Arguments[0];
2292+
const Type *RetTy = GR->getTypeForSPIRVType(Call->ReturnType);
2293+
bool IsSRet = RetTy->isVoidTy();
2294+
2295+
if (IsSRet) {
2296+
const LLT ValTy = MRI->getType(InputReg);
2297+
Register ActualRetValReg = MRI->createGenericVirtualRegister(ValTy);
2298+
SPIRVType *InstructionType =
2299+
GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
2300+
InputReg = Call->Arguments[1];
2301+
auto InputType = GR->getTypeForSPIRVType(GR->getSPIRVTypeForVReg(InputReg));
2302+
Register PtrInputReg;
2303+
if (InputType->getTypeID() == llvm::Type::TypeID::TypedPointerTyID) {
2304+
LLT InputLLT = MRI->getType(InputReg);
2305+
PtrInputReg = MRI->createGenericVirtualRegister(InputLLT);
2306+
SPIRVType *PtrType =
2307+
GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
2308+
MachineMemOperand *MMO1 = MIRBuilder.getMF().getMachineMemOperand(
2309+
MachinePointerInfo(), MachineMemOperand::MOLoad,
2310+
InputLLT.getSizeInBytes(), Align(4));
2311+
MIRBuilder.buildLoad(PtrInputReg, InputReg, *MMO1);
2312+
MRI->setRegClass(PtrInputReg, &SPIRV::iIDRegClass);
2313+
GR->assignSPIRVTypeToVReg(PtrType, PtrInputReg, MIRBuilder.getMF());
2314+
}
2315+
2316+
for (unsigned index = 2; index < 7; index++) {
2317+
ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
2318+
}
2319+
2320+
// Emit the instruction
2321+
auto MIB = MIRBuilder.buildInstr(Opcode)
2322+
.addDef(ActualRetValReg)
2323+
.addUse(GR->getSPIRVTypeID(InstructionType));
2324+
if (PtrInputReg)
2325+
MIB.addUse(PtrInputReg);
2326+
else
2327+
MIB.addUse(InputReg);
2328+
2329+
for (uint32_t Imm : ImmArgs)
2330+
MIB.addImm(Imm);
2331+
unsigned Size = ValTy.getSizeInBytes();
2332+
// Store result to the pointer passed in Arg[0]
2333+
MachineMemOperand *MMO = MIRBuilder.getMF().getMachineMemOperand(
2334+
MachinePointerInfo(), MachineMemOperand::MOStore, Size, Align(4));
2335+
MRI->setRegClass(ActualRetValReg, &SPIRV::pIDRegClass);
2336+
MIRBuilder.buildStore(ActualRetValReg, Call->Arguments[0], *MMO);
2337+
return true;
2338+
} else {
2339+
for (unsigned index = 1; index < 6; index++)
2340+
ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
2341+
2342+
return buildOpFromWrapper(MIRBuilder, Opcode, Call,
2343+
GR->getSPIRVTypeID(Call->ReturnType), ImmArgs);
2344+
}
2345+
}
2346+
2347+
static bool generateAPFixedPointInst(const SPIRV::IncomingCall *Call,
2348+
MachineIRBuilder &MIRBuilder,
2349+
SPIRVGlobalRegistry *GR) {
2350+
const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
2351+
unsigned Opcode =
2352+
SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
2353+
2354+
return buildAPFixedPointInst(Call, Opcode, MIRBuilder, GR);
2355+
}
2356+
22852357
static bool
22862358
generateTernaryBitwiseFunctionINTELInst(const SPIRV::IncomingCall *Call,
22872359
MachineIRBuilder &MIRBuilder,
@@ -2875,6 +2947,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
28752947
return generateExtendedBitOpsInst(Call.get(), MIRBuilder, GR);
28762948
case SPIRV::BindlessINTEL:
28772949
return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
2950+
case SPIRV::ArbitraryPrecisionFixedPoint:
2951+
return generateAPFixedPointInst(Call.get(), MIRBuilder, GR);
28782952
case SPIRV::TernaryBitwiseINTEL:
28792953
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
28802954
}

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.td‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@ def ICarryBorrow : BuiltinGroup;
6868
def ExtendedBitOps : BuiltinGroup;
6969
def BindlessINTEL : BuiltinGroup;
7070
def TernaryBitwiseINTEL : BuiltinGroup;
71+
def ArbitraryPrecisionFixedPoint : BuiltinGroup;
7172

7273
//===----------------------------------------------------------------------===//
7374
// Class defining a demangled builtin record. The information in the record
@@ -1132,6 +1133,19 @@ defm : DemangledNativeBuiltin<"clock_read_hilo_device", OpenCL_std, KernelClock,
11321133
defm : DemangledNativeBuiltin<"clock_read_hilo_work_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
11331134
defm : DemangledNativeBuiltin<"clock_read_hilo_sub_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
11341135

1136+
//SPV_INTEL_arbitrary_precision_fixed_point
1137+
defm : DemangledNativeBuiltin<"__spirv_FixedSqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSqrtINTEL>;
1138+
defm : DemangledNativeBuiltin<"__spirv_FixedRecipINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRecipINTEL>;
1139+
defm : DemangledNativeBuiltin<"__spirv_FixedRsqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRsqrtINTEL>;
1140+
defm : DemangledNativeBuiltin<"__spirv_FixedSinINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinINTEL>;
1141+
defm : DemangledNativeBuiltin<"__spirv_FixedCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosINTEL>;
1142+
defm : DemangledNativeBuiltin<"__spirv_FixedSinCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosINTEL>;
1143+
defm : DemangledNativeBuiltin<"__spirv_FixedSinPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinPiINTEL>;
1144+
defm : DemangledNativeBuiltin<"__spirv_FixedCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosPiINTEL>;
1145+
defm : DemangledNativeBuiltin<"__spirv_FixedSinCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosPiINTEL>;
1146+
defm : DemangledNativeBuiltin<"__spirv_FixedLogINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedLogINTEL>;
1147+
defm : DemangledNativeBuiltin<"__spirv_FixedExpINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedExpINTEL>;
1148+
11351149
//===----------------------------------------------------------------------===//
11361150
// Class defining an atomic instruction on floating-point numbers.
11371151
//

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,10 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
9494
{"SPV_INTEL_fp_max_error",
9595
SPIRV::Extension::Extension::SPV_INTEL_fp_max_error},
9696
{"SPV_INTEL_ternary_bitwise_function",
97-
SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function}};
97+
SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
98+
{"SPV_INTEL_arbitrary_precision_fixed_point",
99+
SPIRV::Extension::Extension::
100+
SPV_INTEL_arbitrary_precision_fixed_point}};
98101

99102
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
100103
StringRef ArgValue,

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -932,3 +932,27 @@ def OpAliasScopeListDeclINTEL: Op<5913, (outs ID:$res), (ins variable_ops),
932932
// SPV_INTEL_ternary_bitwise_function
933933
def OpBitwiseFunctionINTEL: Op<6242, (outs ID:$res), (ins TYPE:$type, ID:$a, ID:$b, ID:$c, ID:$lut_index),
934934
"$res = OpBitwiseFunctionINTEL $type $a $b $c $lut_index">;
935+
936+
//SPV_INTEL_arbitrary_precision_fixed_point
937+
def OpFixedSqrtINTEL: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
938+
"$res = OpFixedSqrtINTEL $result_type $input $sign $l $rl $q $o">;
939+
def OpFixedRecipINTEL: Op<5924, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
940+
"$res = OpFixedRecipINTEL $result_type $input $sign $l $rl $q $o">;
941+
def OpFixedRsqrtINTEL: Op<5925, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
942+
"$res = OpFixedRsqrtINTEL $result_type $input $sign $l $rl $q $o">;
943+
def OpFixedSinINTEL: Op<5926, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
944+
"$res = OpFixedSinINTEL $result_type $input $sign $l $rl $q $o">;
945+
def OpFixedCosINTEL: Op<5927, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
946+
"$res = OpFixedCosINTEL $result_type $input $sign $l $rl $q $o">;
947+
def OpFixedSinCosINTEL: Op<5928, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
948+
"$res = OpFixedSinCosINTEL $result_type $input $sign $l $rl $q $o">;
949+
def OpFixedSinPiINTEL: Op<5929, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
950+
"$res = OpFixedSinPiINTEL $result_type $input $sign $l $rl $q $o">;
951+
def OpFixedCosPiINTEL: Op<5930, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
952+
"$res = OpFixedCosPiINTEL $result_type $input $sign $l $rl $q $o">;
953+
def OpFixedSinCosPiINTEL: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
954+
"$res = OpFixedSinCosPiINTEL $result_type $input $sign $l $rl $q $o">;
955+
def OpFixedLogINTEL: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
956+
"$res = OpFixedLogINTEL $result_type $input $sign $l $rl $q $o">;
957+
def OpFixedExpINTEL: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
958+
"$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1516,6 +1516,27 @@ void addInstrRequirements(const MachineInstr &MI,
15161516
Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR);
15171517
Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
15181518
break;
1519+
case SPIRV::OpFixedCosINTEL:
1520+
case SPIRV::OpFixedSinINTEL:
1521+
case SPIRV::OpFixedCosPiINTEL:
1522+
case SPIRV::OpFixedSinPiINTEL:
1523+
case SPIRV::OpFixedExpINTEL:
1524+
case SPIRV::OpFixedLogINTEL:
1525+
case SPIRV::OpFixedRecipINTEL:
1526+
case SPIRV::OpFixedSqrtINTEL:
1527+
case SPIRV::OpFixedSinCosINTEL:
1528+
case SPIRV::OpFixedSinCosPiINTEL:
1529+
case SPIRV::OpFixedRsqrtINTEL:
1530+
if (!ST.canUseExtension(
1531+
SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point))
1532+
report_fatal_error("This instruction requires the "
1533+
"following SPIR-V extension: "
1534+
"SPV_INTEL_arbitrary_precision_fixed_point",
1535+
false);
1536+
Reqs.addExtension(
1537+
SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point);
1538+
Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFixedPointINTEL);
1539+
break;
15191540
case SPIRV::OpGroupIMulKHR:
15201541
case SPIRV::OpGroupFMulKHR:
15211542
case SPIRV::OpGroupBitwiseAndKHR:

‎llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -314,6 +314,7 @@ defm SPV_INTEL_long_composites : ExtensionOperand<117>;
314314
defm SPV_INTEL_memory_access_aliasing : ExtensionOperand<118>;
315315
defm SPV_INTEL_fp_max_error : ExtensionOperand<119>;
316316
defm SPV_INTEL_ternary_bitwise_function : ExtensionOperand<120>;
317+
defm SPV_INTEL_arbitrary_precision_fixed_point : ExtensionOperand<121>;
317318

318319
//===----------------------------------------------------------------------===//
319320
// Multiclass used to define Capabilities enum values and at the same time
@@ -515,6 +516,7 @@ defm BindlessImagesINTEL : CapabilityOperand<6528, 0, 0, [SPV_INTEL_bindless_ima
515516
defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory_access_aliasing], []>;
516517
defm FPMaxErrorINTEL : CapabilityOperand<6169, 0, 0, [SPV_INTEL_fp_max_error], []>;
517518
defm TernaryBitwiseFunctionINTEL : CapabilityOperand<6241, 0, 0, [SPV_INTEL_ternary_bitwise_function], []>;
519+
defm ArbitraryPrecisionFixedPointINTEL : CapabilityOperand<5922, 0, 0, [SPV_INTEL_arbitrary_precision_fixed_point], []>;
518520

519521
//===----------------------------------------------------------------------===//
520522
// Multiclass used to define SourceLanguage enum values and at the same time

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