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[NFC][SimplifyCFG] Simplify operators for the combined predicate in mergeConditionalStoreToAddress 
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3 files changed

+34
-65
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3 files changed

+34
-65
lines changed

‎llvm/lib/Transforms/Utils/SimplifyCFG.cpp‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4387,10 +4387,12 @@ static bool mergeConditionalStoreToAddress(
43874387

43884388
// OK, we're going to sink the stores to PostBB. The store has to be
43894389
// conditional though, so first create the predicate.
4390-
Value *PCond = cast<BranchInst>(PFB->getSinglePredecessor()->getTerminator())
4391-
->getCondition();
4392-
Value *QCond = cast<BranchInst>(QFB->getSinglePredecessor()->getTerminator())
4393-
->getCondition();
4390+
BranchInst *const PBranch =
4391+
cast<BranchInst>(PFB->getSinglePredecessor()->getTerminator());
4392+
BranchInst *const QBranch =
4393+
cast<BranchInst>(QFB->getSinglePredecessor()->getTerminator());
4394+
Value *const PCond = PBranch->getCondition();
4395+
Value *const QCond = QBranch->getCondition();
43944396

43954397
Value *PPHI = ensureValueAvailableInSuccessor(PStore->getValueOperand(),
43964398
PStore->getParent());
@@ -4401,13 +4403,11 @@ static bool mergeConditionalStoreToAddress(
44014403
IRBuilder<> QB(PostBB, PostBBFirst);
44024404
QB.SetCurrentDebugLocation(PostBBFirst->getStableDebugLoc());
44034405

4404-
Value *PPred = PStore->getParent() == PTB ? PCond : QB.CreateNot(PCond);
4405-
Value *QPred = QStore->getParent() == QTB ? QCond : QB.CreateNot(QCond);
4406+
InvertPCond = (PStore->getParent() == PTB) ^ InvertPCond;
4407+
InvertQCond = (QStore->getParent() == QTB) ^ InvertQCond;
4408+
Value *const PPred = InvertPCond ? PCond : QB.CreateNot(PCond);
4409+
Value *const QPred = InvertQCond ? QCond : QB.CreateNot(QCond);
44064410

4407-
if (InvertPCond)
4408-
PPred = QB.CreateNot(PPred);
4409-
if (InvertQCond)
4410-
QPred = QB.CreateNot(QPred);
44114411
Value *CombinedPred = QB.CreateOr(PPred, QPred);
44124412

44134413
BasicBlock::iterator InsertPt = QB.GetInsertPoint();

‎llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll‎

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -973,9 +973,9 @@ define void @test_widen_exp_v2(ptr noalias %p2, ptr noalias %p, i64 %n) #5 {
973973
; TFA_INTERLEAVE-NEXT: [[ACTIVE_LANE_MASK_ENTRY1:%.*]] = icmp ult i64 1, [[TMP0]]
974974
; TFA_INTERLEAVE-NEXT: br label %[[VECTOR_BODY:.*]]
975975
; TFA_INTERLEAVE: [[VECTOR_BODY]]:
976-
; TFA_INTERLEAVE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[TMP19:.*]] ]
977-
; TFA_INTERLEAVE-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi i1 [ [[ACTIVE_LANE_MASK_ENTRY]], %[[ENTRY]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[TMP19]] ]
978-
; TFA_INTERLEAVE-NEXT: [[ACTIVE_LANE_MASK2:%.*]] = phi i1 [ [[ACTIVE_LANE_MASK_ENTRY1]], %[[ENTRY]] ], [ [[ACTIVE_LANE_MASK_NEXT6:%.*]], %[[TMP19]] ]
976+
; TFA_INTERLEAVE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[TMP15:.*]] ]
977+
; TFA_INTERLEAVE-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi i1 [ [[ACTIVE_LANE_MASK_ENTRY]], %[[ENTRY]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[TMP15]] ]
978+
; TFA_INTERLEAVE-NEXT: [[ACTIVE_LANE_MASK2:%.*]] = phi i1 [ [[ACTIVE_LANE_MASK_ENTRY1]], %[[ENTRY]] ], [ [[ACTIVE_LANE_MASK_NEXT6:%.*]], %[[TMP15]] ]
979979
; TFA_INTERLEAVE-NEXT: [[TMP4:%.*]] = load double, ptr [[P2]], align 8
980980
; TFA_INTERLEAVE-NEXT: [[TMP5:%.*]] = tail call double @llvm.exp.f64(double [[TMP4]]) #[[ATTR7:[0-9]+]]
981981
; TFA_INTERLEAVE-NEXT: [[TMP6:%.*]] = tail call double @llvm.exp.f64(double [[TMP4]]) #[[ATTR7]]
@@ -988,16 +988,12 @@ define void @test_widen_exp_v2(ptr noalias %p2, ptr noalias %p, i64 %n) #5 {
988988
; TFA_INTERLEAVE-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP11]], double 1.000000e+00, double 0.000000e+00
989989
; TFA_INTERLEAVE-NEXT: [[PREDPHI3:%.*]] = select i1 [[TMP12]], double 1.000000e+00, double 0.000000e+00
990990
; TFA_INTERLEAVE-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[ACTIVE_LANE_MASK2]], double [[PREDPHI3]], double [[PREDPHI]]
991-
; TFA_INTERLEAVE-NEXT: [[TMP13:%.*]] = xor i1 [[ACTIVE_LANE_MASK]], true
992-
; TFA_INTERLEAVE-NEXT: [[TMP14:%.*]] = xor i1 [[ACTIVE_LANE_MASK2]], true
993-
; TFA_INTERLEAVE-NEXT: [[TMP15:%.*]] = xor i1 [[TMP13]], true
994-
; TFA_INTERLEAVE-NEXT: [[TMP16:%.*]] = xor i1 [[TMP14]], true
995-
; TFA_INTERLEAVE-NEXT: [[TMP17:%.*]] = or i1 [[TMP15]], [[TMP16]]
996-
; TFA_INTERLEAVE-NEXT: br i1 [[TMP17]], label %[[BB18:.*]], label %[[TMP19]]
997-
; TFA_INTERLEAVE: [[BB18]]:
991+
; TFA_INTERLEAVE-NEXT: [[TMP13:%.*]] = or i1 [[ACTIVE_LANE_MASK]], [[ACTIVE_LANE_MASK2]]
992+
; TFA_INTERLEAVE-NEXT: br i1 [[TMP13]], label %[[BB14:.*]], label %[[TMP15]]
993+
; TFA_INTERLEAVE: [[BB14]]:
998994
; TFA_INTERLEAVE-NEXT: store double [[SPEC_SELECT]], ptr [[P]], align 8
999-
; TFA_INTERLEAVE-NEXT: br label %[[TMP19]]
1000-
; TFA_INTERLEAVE: [[TMP19]]:
995+
; TFA_INTERLEAVE-NEXT: br label %[[TMP15]]
996+
; TFA_INTERLEAVE: [[TMP15]]:
1001997
; TFA_INTERLEAVE-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 2
1002998
; TFA_INTERLEAVE-NEXT: [[TMP20:%.*]] = add i64 [[INDEX]], 1
1003999
; TFA_INTERLEAVE-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = icmp ult i64 [[INDEX]], [[TMP3]]

‎llvm/test/Transforms/SimplifyCFG/merge-cond-stores-2.ll‎

Lines changed: 16 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 5
22
; RUN: opt -S < %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -simplifycfg-merge-cond-stores=true -simplifycfg-merge-cond-stores-aggressively=false -phi-node-folding-threshold=1 | FileCheck %s
33

44
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
@@ -9,9 +9,10 @@ target triple = "armv7--linux-gnueabihf"
99
; block and there should be no PHIs.
1010

1111
define i32 @f(ptr %b) {
12-
; CHECK-LABEL: @f(
13-
; CHECK-NEXT: entry:
14-
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 4
12+
; CHECK-LABEL: define i32 @f(
13+
; CHECK-SAME: ptr [[B:%.*]]) {
14+
; CHECK-NEXT: [[ENTRY:.*:]]
15+
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B]], align 4
1516
; CHECK-NEXT: [[AND:%.*]] = and i32 [[TMP0]], 1
1617
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[AND]], 0
1718
; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP0]], -2147483648
@@ -27,119 +28,91 @@ define i32 @f(ptr %b) {
2728
; CHECK-NEXT: [[TOBOOL7:%.*]] = icmp eq i32 [[AND6]], 0
2829
; CHECK-NEXT: [[OR9:%.*]] = or i32 [[TMP2]], 536870912
2930
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL7]], i32 [[TMP2]], i32 [[OR9]]
30-
; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[TMP5]], true
3131
; CHECK-NEXT: [[TMP7:%.*]] = xor i1 [[TOBOOL7]], true
32-
; CHECK-NEXT: [[TMP8:%.*]] = xor i1 [[TMP6]], true
33-
; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[TMP8]], [[TMP7]]
32+
; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP5]], [[TMP7]]
3433
; CHECK-NEXT: [[AND11:%.*]] = and i32 [[SPEC_SELECT]], 8
3534
; CHECK-NEXT: [[TOBOOL12:%.*]] = icmp eq i32 [[AND11]], 0
3635
; CHECK-NEXT: [[OR14:%.*]] = or i32 [[SPEC_SELECT]], 268435456
3736
; CHECK-NEXT: [[SPEC_SELECT1:%.*]] = select i1 [[TOBOOL12]], i32 [[SPEC_SELECT]], i32 [[OR14]]
38-
; CHECK-NEXT: [[TMP10:%.*]] = xor i1 [[TMP9]], true
3937
; CHECK-NEXT: [[TMP11:%.*]] = xor i1 [[TOBOOL12]], true
40-
; CHECK-NEXT: [[TMP12:%.*]] = xor i1 [[TMP10]], true
4138
; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP12]], [[TMP11]]
4239
; CHECK-NEXT: [[AND16:%.*]] = and i32 [[SPEC_SELECT1]], 16
4340
; CHECK-NEXT: [[TOBOOL17:%.*]] = icmp eq i32 [[AND16]], 0
4441
; CHECK-NEXT: [[OR19:%.*]] = or i32 [[SPEC_SELECT1]], 134217728
4542
; CHECK-NEXT: [[SPEC_SELECT2:%.*]] = select i1 [[TOBOOL17]], i32 [[SPEC_SELECT1]], i32 [[OR19]]
46-
; CHECK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP13]], true
4743
; CHECK-NEXT: [[TMP15:%.*]] = xor i1 [[TOBOOL17]], true
48-
; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP14]], true
49-
; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP16]], [[TMP15]]
44+
; CHECK-NEXT: [[TMP20:%.*]] = or i1 [[TMP13]], [[TMP15]]
5045
; CHECK-NEXT: [[AND21:%.*]] = and i32 [[SPEC_SELECT2]], 32
5146
; CHECK-NEXT: [[TOBOOL22:%.*]] = icmp eq i32 [[AND21]], 0
5247
; CHECK-NEXT: [[OR24:%.*]] = or i32 [[SPEC_SELECT2]], 67108864
5348
; CHECK-NEXT: [[SPEC_SELECT3:%.*]] = select i1 [[TOBOOL22]], i32 [[SPEC_SELECT2]], i32 [[OR24]]
54-
; CHECK-NEXT: [[TMP18:%.*]] = xor i1 [[TMP17]], true
5549
; CHECK-NEXT: [[TMP19:%.*]] = xor i1 [[TOBOOL22]], true
56-
; CHECK-NEXT: [[TMP20:%.*]] = xor i1 [[TMP18]], true
5750
; CHECK-NEXT: [[TMP21:%.*]] = or i1 [[TMP20]], [[TMP19]]
5851
; CHECK-NEXT: [[AND26:%.*]] = and i32 [[SPEC_SELECT3]], 64
5952
; CHECK-NEXT: [[TOBOOL27:%.*]] = icmp eq i32 [[AND26]], 0
6053
; CHECK-NEXT: [[OR29:%.*]] = or i32 [[SPEC_SELECT3]], 33554432
6154
; CHECK-NEXT: [[SPEC_SELECT4:%.*]] = select i1 [[TOBOOL27]], i32 [[SPEC_SELECT3]], i32 [[OR29]]
62-
; CHECK-NEXT: [[TMP22:%.*]] = xor i1 [[TMP21]], true
6355
; CHECK-NEXT: [[TMP23:%.*]] = xor i1 [[TOBOOL27]], true
64-
; CHECK-NEXT: [[TMP24:%.*]] = xor i1 [[TMP22]], true
65-
; CHECK-NEXT: [[TMP25:%.*]] = or i1 [[TMP24]], [[TMP23]]
56+
; CHECK-NEXT: [[TMP28:%.*]] = or i1 [[TMP21]], [[TMP23]]
6657
; CHECK-NEXT: [[AND31:%.*]] = and i32 [[SPEC_SELECT4]], 256
6758
; CHECK-NEXT: [[TOBOOL32:%.*]] = icmp eq i32 [[AND31]], 0
6859
; CHECK-NEXT: [[OR34:%.*]] = or i32 [[SPEC_SELECT4]], 8388608
6960
; CHECK-NEXT: [[SPEC_SELECT5:%.*]] = select i1 [[TOBOOL32]], i32 [[SPEC_SELECT4]], i32 [[OR34]]
70-
; CHECK-NEXT: [[TMP26:%.*]] = xor i1 [[TMP25]], true
7161
; CHECK-NEXT: [[TMP27:%.*]] = xor i1 [[TOBOOL32]], true
72-
; CHECK-NEXT: [[TMP28:%.*]] = xor i1 [[TMP26]], true
7362
; CHECK-NEXT: [[TMP29:%.*]] = or i1 [[TMP28]], [[TMP27]]
7463
; CHECK-NEXT: [[AND36:%.*]] = and i32 [[SPEC_SELECT5]], 512
7564
; CHECK-NEXT: [[TOBOOL37:%.*]] = icmp eq i32 [[AND36]], 0
7665
; CHECK-NEXT: [[OR39:%.*]] = or i32 [[SPEC_SELECT5]], 4194304
7766
; CHECK-NEXT: [[SPEC_SELECT6:%.*]] = select i1 [[TOBOOL37]], i32 [[SPEC_SELECT5]], i32 [[OR39]]
78-
; CHECK-NEXT: [[TMP30:%.*]] = xor i1 [[TMP29]], true
7967
; CHECK-NEXT: [[TMP31:%.*]] = xor i1 [[TOBOOL37]], true
80-
; CHECK-NEXT: [[TMP32:%.*]] = xor i1 [[TMP30]], true
81-
; CHECK-NEXT: [[TMP33:%.*]] = or i1 [[TMP32]], [[TMP31]]
68+
; CHECK-NEXT: [[TMP36:%.*]] = or i1 [[TMP29]], [[TMP31]]
8269
; CHECK-NEXT: [[AND41:%.*]] = and i32 [[SPEC_SELECT6]], 1024
8370
; CHECK-NEXT: [[TOBOOL42:%.*]] = icmp eq i32 [[AND41]], 0
8471
; CHECK-NEXT: [[OR44:%.*]] = or i32 [[SPEC_SELECT6]], 2097152
8572
; CHECK-NEXT: [[SPEC_SELECT7:%.*]] = select i1 [[TOBOOL42]], i32 [[SPEC_SELECT6]], i32 [[OR44]]
86-
; CHECK-NEXT: [[TMP34:%.*]] = xor i1 [[TMP33]], true
8773
; CHECK-NEXT: [[TMP35:%.*]] = xor i1 [[TOBOOL42]], true
88-
; CHECK-NEXT: [[TMP36:%.*]] = xor i1 [[TMP34]], true
8974
; CHECK-NEXT: [[TMP37:%.*]] = or i1 [[TMP36]], [[TMP35]]
9075
; CHECK-NEXT: [[AND46:%.*]] = and i32 [[SPEC_SELECT7]], 2048
9176
; CHECK-NEXT: [[TOBOOL47:%.*]] = icmp eq i32 [[AND46]], 0
9277
; CHECK-NEXT: [[OR49:%.*]] = or i32 [[SPEC_SELECT7]], 1048576
9378
; CHECK-NEXT: [[SPEC_SELECT8:%.*]] = select i1 [[TOBOOL47]], i32 [[SPEC_SELECT7]], i32 [[OR49]]
94-
; CHECK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP37]], true
9579
; CHECK-NEXT: [[TMP39:%.*]] = xor i1 [[TOBOOL47]], true
96-
; CHECK-NEXT: [[TMP40:%.*]] = xor i1 [[TMP38]], true
97-
; CHECK-NEXT: [[TMP41:%.*]] = or i1 [[TMP40]], [[TMP39]]
80+
; CHECK-NEXT: [[TMP44:%.*]] = or i1 [[TMP37]], [[TMP39]]
9881
; CHECK-NEXT: [[AND51:%.*]] = and i32 [[SPEC_SELECT8]], 4096
9982
; CHECK-NEXT: [[TOBOOL52:%.*]] = icmp eq i32 [[AND51]], 0
10083
; CHECK-NEXT: [[OR54:%.*]] = or i32 [[SPEC_SELECT8]], 524288
10184
; CHECK-NEXT: [[SPEC_SELECT9:%.*]] = select i1 [[TOBOOL52]], i32 [[SPEC_SELECT8]], i32 [[OR54]]
102-
; CHECK-NEXT: [[TMP42:%.*]] = xor i1 [[TMP41]], true
10385
; CHECK-NEXT: [[TMP43:%.*]] = xor i1 [[TOBOOL52]], true
104-
; CHECK-NEXT: [[TMP44:%.*]] = xor i1 [[TMP42]], true
10586
; CHECK-NEXT: [[TMP45:%.*]] = or i1 [[TMP44]], [[TMP43]]
10687
; CHECK-NEXT: [[AND56:%.*]] = and i32 [[SPEC_SELECT9]], 8192
10788
; CHECK-NEXT: [[TOBOOL57:%.*]] = icmp eq i32 [[AND56]], 0
10889
; CHECK-NEXT: [[OR59:%.*]] = or i32 [[SPEC_SELECT9]], 262144
10990
; CHECK-NEXT: [[SPEC_SELECT10:%.*]] = select i1 [[TOBOOL57]], i32 [[SPEC_SELECT9]], i32 [[OR59]]
110-
; CHECK-NEXT: [[TMP46:%.*]] = xor i1 [[TMP45]], true
11191
; CHECK-NEXT: [[TMP47:%.*]] = xor i1 [[TOBOOL57]], true
112-
; CHECK-NEXT: [[TMP48:%.*]] = xor i1 [[TMP46]], true
113-
; CHECK-NEXT: [[TMP49:%.*]] = or i1 [[TMP48]], [[TMP47]]
92+
; CHECK-NEXT: [[TMP52:%.*]] = or i1 [[TMP45]], [[TMP47]]
11493
; CHECK-NEXT: [[AND61:%.*]] = and i32 [[SPEC_SELECT10]], 16384
11594
; CHECK-NEXT: [[TOBOOL62:%.*]] = icmp eq i32 [[AND61]], 0
11695
; CHECK-NEXT: [[OR64:%.*]] = or i32 [[SPEC_SELECT10]], 131072
11796
; CHECK-NEXT: [[SPEC_SELECT11:%.*]] = select i1 [[TOBOOL62]], i32 [[SPEC_SELECT10]], i32 [[OR64]]
118-
; CHECK-NEXT: [[TMP50:%.*]] = xor i1 [[TMP49]], true
11997
; CHECK-NEXT: [[TMP51:%.*]] = xor i1 [[TOBOOL62]], true
120-
; CHECK-NEXT: [[TMP52:%.*]] = xor i1 [[TMP50]], true
12198
; CHECK-NEXT: [[TMP53:%.*]] = or i1 [[TMP52]], [[TMP51]]
12299
; CHECK-NEXT: [[AND66:%.*]] = and i32 [[SPEC_SELECT11]], 32768
123100
; CHECK-NEXT: [[TOBOOL67:%.*]] = icmp eq i32 [[AND66]], 0
124101
; CHECK-NEXT: [[OR69:%.*]] = or i32 [[SPEC_SELECT11]], 65536
125102
; CHECK-NEXT: [[SPEC_SELECT12:%.*]] = select i1 [[TOBOOL67]], i32 [[SPEC_SELECT11]], i32 [[OR69]]
126-
; CHECK-NEXT: [[TMP54:%.*]] = xor i1 [[TMP53]], true
127103
; CHECK-NEXT: [[TMP55:%.*]] = xor i1 [[TOBOOL67]], true
128-
; CHECK-NEXT: [[TMP56:%.*]] = xor i1 [[TMP54]], true
129-
; CHECK-NEXT: [[TMP57:%.*]] = or i1 [[TMP56]], [[TMP55]]
104+
; CHECK-NEXT: [[TMP60:%.*]] = or i1 [[TMP53]], [[TMP55]]
130105
; CHECK-NEXT: [[AND71:%.*]] = and i32 [[SPEC_SELECT12]], 128
131106
; CHECK-NEXT: [[TOBOOL72:%.*]] = icmp eq i32 [[AND71]], 0
132107
; CHECK-NEXT: [[OR74:%.*]] = or i32 [[SPEC_SELECT12]], 16777216
133108
; CHECK-NEXT: [[SPEC_SELECT13:%.*]] = select i1 [[TOBOOL72]], i32 [[SPEC_SELECT12]], i32 [[OR74]]
134-
; CHECK-NEXT: [[TMP58:%.*]] = xor i1 [[TMP57]], true
135109
; CHECK-NEXT: [[TMP59:%.*]] = xor i1 [[TOBOOL72]], true
136-
; CHECK-NEXT: [[TMP60:%.*]] = xor i1 [[TMP58]], true
137110
; CHECK-NEXT: [[TMP61:%.*]] = or i1 [[TMP60]], [[TMP59]]
138-
; CHECK-NEXT: br i1 [[TMP61]], label [[TMP62:%.*]], label [[TMP63:%.*]]
139-
; CHECK: 62:
111+
; CHECK-NEXT: br i1 [[TMP61]], label %[[BB34:.*]], label %[[BB35:.*]]
112+
; CHECK: [[BB34]]:
140113
; CHECK-NEXT: store i32 [[SPEC_SELECT13]], ptr [[B]], align 4
141-
; CHECK-NEXT: br label [[TMP63]]
142-
; CHECK: 63:
114+
; CHECK-NEXT: br label %[[BB35]]
115+
; CHECK: [[BB35]]:
143116
; CHECK-NEXT: ret i32 0
144117
;
145118
entry:

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