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[RISCV] Support FrameIndex operands in getMemOperandsWithOffsetWidth / getMemOperandWithOffsetWidth (#73802)
I noted AArch64 happily accepts a FrameIndex operand as well as a register. This doesn't cause any changes outside of my C++ unit test for the current state of in-tree, but this will cause additional test changes if #73789 is rebased on top of it. Note that the returned Offset doesn't seem at all as meaningful if you have a FrameIndex base, though the approach taken here follows AArch64 (see D54847). This change won't harm the approach taken in shouldClusterMemOps because memOpsHaveSameBasePtr will only return true if the FrameIndex operand is the same for both operations.
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6 files changed

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6 files changed

+52
-46
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2304,7 +2304,8 @@ bool RISCVInstrInfo::getMemOperandWithOffsetWidth(
23042304
// load/store instructions.
23052305
if (LdSt.getNumExplicitOperands() != 3)
23062306
return false;
2307-
if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm())
2307+
if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) ||
2308+
!LdSt.getOperand(2).isImm())
23082309
return false;
23092310

23102311
if (!LdSt.hasOneMemOperand())

‎llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -364,8 +364,8 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
364364
; RV32I-FPELIM-NEXT: sw zero, 16(sp)
365365
; RV32I-FPELIM-NEXT: sw zero, 52(sp)
366366
; RV32I-FPELIM-NEXT: sw zero, 48(sp)
367-
; RV32I-FPELIM-NEXT: sw zero, 44(sp)
368-
; RV32I-FPELIM-NEXT: li t0, 8
367+
; RV32I-FPELIM-NEXT: li a0, 8
368+
; RV32I-FPELIM-NEXT: sw a0, 40(sp)
369369
; RV32I-FPELIM-NEXT: li a0, 1
370370
; RV32I-FPELIM-NEXT: li a1, 2
371371
; RV32I-FPELIM-NEXT: li a2, 3
@@ -374,7 +374,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
374374
; RV32I-FPELIM-NEXT: li a5, 6
375375
; RV32I-FPELIM-NEXT: li a6, 7
376376
; RV32I-FPELIM-NEXT: addi a7, sp, 40
377-
; RV32I-FPELIM-NEXT: sw t0, 40(sp)
377+
; RV32I-FPELIM-NEXT: sw zero, 44(sp)
378378
; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs@plt
379379
; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
380380
; RV32I-FPELIM-NEXT: addi sp, sp, 64
@@ -397,8 +397,8 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
397397
; RV32I-WITHFP-NEXT: sw zero, -48(s0)
398398
; RV32I-WITHFP-NEXT: sw zero, -12(s0)
399399
; RV32I-WITHFP-NEXT: sw zero, -16(s0)
400-
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
401-
; RV32I-WITHFP-NEXT: li t0, 8
400+
; RV32I-WITHFP-NEXT: li a0, 8
401+
; RV32I-WITHFP-NEXT: sw a0, -24(s0)
402402
; RV32I-WITHFP-NEXT: li a0, 1
403403
; RV32I-WITHFP-NEXT: li a1, 2
404404
; RV32I-WITHFP-NEXT: li a2, 3
@@ -407,7 +407,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
407407
; RV32I-WITHFP-NEXT: li a5, 6
408408
; RV32I-WITHFP-NEXT: li a6, 7
409409
; RV32I-WITHFP-NEXT: addi a7, s0, -24
410-
; RV32I-WITHFP-NEXT: sw t0, -24(s0)
410+
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
411411
; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs@plt
412412
; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
413413
; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload

‎llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -140,11 +140,11 @@ define i64 @caller_large_scalars() nounwind {
140140
; RV64I-NEXT: sd a0, 0(sp)
141141
; RV64I-NEXT: sd zero, 56(sp)
142142
; RV64I-NEXT: sd zero, 48(sp)
143-
; RV64I-NEXT: sd zero, 40(sp)
144-
; RV64I-NEXT: li a2, 1
143+
; RV64I-NEXT: li a0, 1
144+
; RV64I-NEXT: sd a0, 32(sp)
145145
; RV64I-NEXT: addi a0, sp, 32
146146
; RV64I-NEXT: mv a1, sp
147-
; RV64I-NEXT: sd a2, 32(sp)
147+
; RV64I-NEXT: sd zero, 40(sp)
148148
; RV64I-NEXT: call callee_large_scalars@plt
149149
; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
150150
; RV64I-NEXT: addi sp, sp, 80
@@ -199,8 +199,8 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
199199
; RV64I-NEXT: sd a0, 16(sp)
200200
; RV64I-NEXT: sd zero, 72(sp)
201201
; RV64I-NEXT: sd zero, 64(sp)
202-
; RV64I-NEXT: sd zero, 56(sp)
203-
; RV64I-NEXT: li t0, 8
202+
; RV64I-NEXT: li a0, 8
203+
; RV64I-NEXT: sd a0, 48(sp)
204204
; RV64I-NEXT: li a0, 1
205205
; RV64I-NEXT: li a1, 2
206206
; RV64I-NEXT: li a2, 3
@@ -209,7 +209,7 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
209209
; RV64I-NEXT: li a5, 6
210210
; RV64I-NEXT: li a6, 7
211211
; RV64I-NEXT: addi a7, sp, 48
212-
; RV64I-NEXT: sd t0, 48(sp)
212+
; RV64I-NEXT: sd zero, 56(sp)
213213
; RV64I-NEXT: call callee_large_scalars_exhausted_regs@plt
214214
; RV64I-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
215215
; RV64I-NEXT: addi sp, sp, 96

‎llvm/test/CodeGen/RISCV/push-pop-popret.ll‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1018,13 +1018,13 @@ define i32 @varargs(ptr %fmt, ...) nounwind {
10181018
; RV64IZCMP-NEXT: sd a1, 24(sp)
10191019
; RV64IZCMP-NEXT: sd a7, 72(sp)
10201020
; RV64IZCMP-NEXT: sd a6, 64(sp)
1021+
; RV64IZCMP-NEXT: addi a0, sp, 28
1022+
; RV64IZCMP-NEXT: sd a0, 8(sp)
1023+
; RV64IZCMP-NEXT: lw a0, 24(sp)
10211024
; RV64IZCMP-NEXT: sd a5, 56(sp)
10221025
; RV64IZCMP-NEXT: sd a4, 48(sp)
10231026
; RV64IZCMP-NEXT: sd a3, 40(sp)
10241027
; RV64IZCMP-NEXT: sd a2, 32(sp)
1025-
; RV64IZCMP-NEXT: addi a0, sp, 28
1026-
; RV64IZCMP-NEXT: sd a0, 8(sp)
1027-
; RV64IZCMP-NEXT: lw a0, 24(sp)
10281028
; RV64IZCMP-NEXT: addi sp, sp, 80
10291029
; RV64IZCMP-NEXT: ret
10301030
;
@@ -1050,13 +1050,13 @@ define i32 @varargs(ptr %fmt, ...) nounwind {
10501050
; RV64IZCMP-SR-NEXT: sd a1, 24(sp)
10511051
; RV64IZCMP-SR-NEXT: sd a7, 72(sp)
10521052
; RV64IZCMP-SR-NEXT: sd a6, 64(sp)
1053+
; RV64IZCMP-SR-NEXT: addi a0, sp, 28
1054+
; RV64IZCMP-SR-NEXT: sd a0, 8(sp)
1055+
; RV64IZCMP-SR-NEXT: lw a0, 24(sp)
10531056
; RV64IZCMP-SR-NEXT: sd a5, 56(sp)
10541057
; RV64IZCMP-SR-NEXT: sd a4, 48(sp)
10551058
; RV64IZCMP-SR-NEXT: sd a3, 40(sp)
10561059
; RV64IZCMP-SR-NEXT: sd a2, 32(sp)
1057-
; RV64IZCMP-SR-NEXT: addi a0, sp, 28
1058-
; RV64IZCMP-SR-NEXT: sd a0, 8(sp)
1059-
; RV64IZCMP-SR-NEXT: lw a0, 24(sp)
10601060
; RV64IZCMP-SR-NEXT: addi sp, sp, 80
10611061
; RV64IZCMP-SR-NEXT: ret
10621062
;
@@ -1082,13 +1082,13 @@ define i32 @varargs(ptr %fmt, ...) nounwind {
10821082
; RV64I-NEXT: sd a1, 24(sp)
10831083
; RV64I-NEXT: sd a7, 72(sp)
10841084
; RV64I-NEXT: sd a6, 64(sp)
1085+
; RV64I-NEXT: addi a0, sp, 28
1086+
; RV64I-NEXT: sd a0, 8(sp)
1087+
; RV64I-NEXT: lw a0, 24(sp)
10851088
; RV64I-NEXT: sd a5, 56(sp)
10861089
; RV64I-NEXT: sd a4, 48(sp)
10871090
; RV64I-NEXT: sd a3, 40(sp)
10881091
; RV64I-NEXT: sd a2, 32(sp)
1089-
; RV64I-NEXT: addi a0, sp, 28
1090-
; RV64I-NEXT: sd a0, 8(sp)
1091-
; RV64I-NEXT: lw a0, 24(sp)
10921092
; RV64I-NEXT: addi sp, sp, 80
10931093
; RV64I-NEXT: ret
10941094
%va = alloca ptr

‎llvm/test/CodeGen/RISCV/vararg.ll‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -104,13 +104,13 @@ define i32 @va1(ptr %fmt, ...) {
104104
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp)
105105
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp)
106106
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp)
107+
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 28
108+
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
109+
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 24(sp)
107110
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp)
108111
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp)
109112
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp)
110113
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp)
111-
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 28
112-
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
113-
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 24(sp)
114114
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
115115
; LP64-LP64F-LP64D-FPELIM-NEXT: ret
116116
;
@@ -127,13 +127,13 @@ define i32 @va1(ptr %fmt, ...) {
127127
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
128128
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
129129
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
130+
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 12
131+
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
132+
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0)
130133
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
131134
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
132135
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
133136
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
134-
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 12
135-
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
136-
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0)
137137
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
138138
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
139139
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
@@ -1773,25 +1773,25 @@ define i32 @va_large_stack(ptr %fmt, ...) {
17731773
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0
17741774
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 320(a0)
17751775
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414
1776-
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0
1777-
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 312(a0)
1778-
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414
1779-
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0
1780-
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 304(a0)
1781-
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414
1782-
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0
1783-
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 296(a0)
1784-
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414
1785-
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0
1786-
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 288(a0)
1787-
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414
17881776
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 284
17891777
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0
17901778
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
17911779
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414
17921780
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0
17931781
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 280(a0)
17941782
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
1783+
; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1
1784+
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 312(a1)
1785+
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
1786+
; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1
1787+
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 304(a1)
1788+
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
1789+
; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1
1790+
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 296(a1)
1791+
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
1792+
; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1
1793+
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 288(a1)
1794+
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
17951795
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a1, a1, 336
17961796
; LP64-LP64F-LP64D-FPELIM-NEXT: add sp, sp, a1
17971797
; LP64-LP64F-LP64D-FPELIM-NEXT: ret
@@ -1812,15 +1812,15 @@ define i32 @va_large_stack(ptr %fmt, ...) {
18121812
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
18131813
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
18141814
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
1815-
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
1816-
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
1817-
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
1818-
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
18191815
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 12
18201816
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 24414
18211817
; LP64-LP64F-LP64D-WITHFP-NEXT: sub a1, s0, a1
18221818
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -288(a1)
18231819
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0)
1820+
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
1821+
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
1822+
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
1823+
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
18241824
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 24414
18251825
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -1680
18261826
; LP64-LP64F-LP64D-WITHFP-NEXT: add sp, sp, a1

‎llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp‎

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,6 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
154154
Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
155155
OffsetIsScalable, Width, TRI);
156156

157-
// TODO: AArch64 can handle this case, and we probably should too.
158157
BaseOps.clear();
159158
MMO = MF->getMachineMemOperand(MachinePointerInfo(),
160159
MachineMemOperand::MOStore, 4, Align(4));
@@ -165,7 +164,13 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
165164
.addMemOperand(MMO);
166165
Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
167166
OffsetIsScalable, Width, TRI);
168-
EXPECT_FALSE(Res);
167+
ASSERT_TRUE(Res);
168+
ASSERT_EQ(BaseOps.size(), 1u);
169+
ASSERT_TRUE(BaseOps.front()->isFI());
170+
EXPECT_EQ(BaseOps.front()->getIndex(), 2);
171+
EXPECT_EQ(Offset, 4);
172+
EXPECT_FALSE(OffsetIsScalable);
173+
EXPECT_EQ(Width, 4u);
169174
}
170175

171176
} // namespace

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