fixup! implement non-VLMAX cases in selectVLOp

Author: michaelmaitland

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

@@ -385,17 +385,21 @@ RISCVInstructionSelector::selectVLOp(MachineOperand &Root) const {
   assert(Root.isReg() && "Expected operand to be a Register");
   MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
 
-  if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT &&
-      RootDef->getOperand(1).getCImm()->getSExtValue() == RISCV::VLMaxSentinel)
-    // If the operand is a G_CONSTANT with value VLMaxSentinel, convert it
-    // to an immediate with value VLMaxSentinel. This is recognized specially by
-    // the vsetvli insertion pass.
-    return {
-        {[=](MachineInstrBuilder &MIB) { MIB.addImm(RISCV::VLMaxSentinel); }}};
-
-  // FIXME: Implement non-VLMAX case. ISEL will fail gracefully by returning
-  // like this for now.
-  return std::nullopt;
+  if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT) {
+    auto C = RootDef->getOperand(1).getCImm();
+    if (C->getSExtValue() == RISCV::VLMaxSentinel || C->getValue().isAllOnes())
+      // If the operand is a G_CONSTANT with value VLMaxSentinel or all ones,
+      // convert it to an immediate with value VLMaxSentinel. This is recognized
+      // specially by the vsetvli insertion pass.
+      return {{[=](MachineInstrBuilder &MIB) {
+        MIB.addImm(RISCV::VLMaxSentinel);
+      }}};
+
+    if (isUInt<5>(C->getZExtValue()))
+      return {
+          {[=](MachineInstrBuilder &MIB) { MIB.addImm(C->getZExtValue()); }}};
+  }
+  return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }}};
 }
 
 InstructionSelector::ComplexRendererFns

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir

@@ -0,0 +1,70 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN:   -verify-machineinstrs %s -o - | FileCheck %s
+
+name:            negative_vl
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    %0:gprb(s32) = G_CONSTANT i32 -2
+    %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+    $v0 = COPY %1(<vscale x 1 x s1>)
+    PseudoRET implicit $v0
+...
+---
+name:            nonconst_vl
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x10
+    ; CHECK-LABEL: name: nonconst_vl
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
+    ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
+    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+    ; CHECK-NEXT: PseudoRET implicit $v0
+    %0:gprb(s32) = COPY $x10
+    %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+    $v0 = COPY %1(<vscale x 1 x s1>)
+    PseudoRET implicit $v0
+...
+
+---
+name:            nonzero_vl
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: nonzero_vl
+    ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
+    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+    ; CHECK-NEXT: PseudoRET implicit $v0
+    %0:gprb(s32) = G_CONSTANT i32 1
+    %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+    $v0 = COPY %1(<vscale x 1 x s1>)
+    PseudoRET implicit $v0
+...
+
+---
+name:            zero_vl
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: zero_vl
+    ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
+    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+    ; CHECK-NEXT: PseudoRET implicit $v0
+    %0:gprb(s32) = G_CONSTANT i32 0
+    %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+    $v0 = COPY %1(<vscale x 1 x s1>)
+    PseudoRET implicit $v0
+...
+