update checks for affected files

Author: himadhith

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -19213,7 +19213,8 @@ static SDValue combineADDToSUB(SDNode *N, SelectionDAG &DAG,
   EVT VT = N->getValueType(0);
 
   // Handle v2i64, v4i32, v8i16 and v16i8 types
-  if (!VT.isVector() || VT.getSizeInBits() != 128)
+  if (!(VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v4i32 ||
+        VT == MVT::v2i64))
     return SDValue();
 
   SDValue LHS = N->getOperand(0);

llvm/test/CodeGen/PowerPC/addition-vector-all-ones.ll

@@ -8,15 +8,14 @@
 ; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc-ibm-aix \
 ; RUN:     -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
 
-; The addition of vector `A` with vector of 1s currently uses `vspltisw` to generate vector of 1s followed by add operation.
+; Optimized version which `xxleqv` and `vsubu` to generate vector of -1s to leverage the identity A - (-1) = A + 1.
 
 ; Function for the vector type v2i64 `a + {1, 1}`
 define <2 x i64> @test_v2i64(<2 x i64> %a) {
 ; CHECK-LABEL: test_v2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vspltisw v3, 1
-; CHECK-NEXT:    vupklsw v3, v3
-; CHECK-NEXT:    vaddudm v2, v2, v3
+; CHECK-NEXT:    xxleqv v3, v3, v3
+; CHECK-NEXT:    vsubudm v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %add = add <2 x i64> %a, splat (i64 1)
@@ -27,8 +26,8 @@ entry:
 define <4 x i32> @test_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: test_v4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vspltisw v3, 1
-; CHECK-NEXT:    vadduwm v2, v2, v3
+; CHECK-NEXT:    xxleqv v3, v3, v3
+; CHECK-NEXT:    vsubuwm v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %add = add <4 x i32> %a, splat (i32 1)
@@ -39,8 +38,8 @@ entry:
 define <8 x i16> @test_v8i16(<8 x i16> %a) {
 ; CHECK-LABEL: test_v8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vspltish v3, 1
-; CHECK-NEXT:    vadduhm v2, v2, v3
+; CHECK-NEXT:    xxleqv v3, v3, v3
+; CHECK-NEXT:    vsubuhm v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %add = add <8 x i16> %a, splat (i16 1)
@@ -51,8 +50,8 @@ entry:
 define <16 x i8> @test_16i8(<16 x i8> %a) {
 ; CHECK-LABEL: test_16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxspltib v3, 1
-; CHECK-NEXT:    vaddubm v2, v2, v3
+; CHECK-NEXT:    xxleqv v3, v3, v3
+; CHECK-NEXT:    vsububm v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %add = add <16 x i8> %a, splat (i8 1)

llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll

@@ -16,17 +16,16 @@ define <2 x i64> @test_add(<2 x i64> %x, <2 x i64> %y) nounwind {
 define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind {
 ; VSX-LABEL: increment_by_one:
 ; VSX:       # %bb.0:
-; VSX-NEXT:    vspltisw 3, 1
-; VSX-NEXT:    vupklsw 3, 3
-; VSX-NEXT:    vaddudm 2, 2, 3
+; VSX-NEXT:    xxleqv 35, 35, 35
+; VSX-NEXT:    vsubudm 2, 2, 3
 ; VSX-NEXT:    blr
 ;
 ; NOVSX-LABEL: increment_by_one:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
 ; NOVSX-NEXT:    addi 3, 3, .LCPI1_0@toc@l
 ; NOVSX-NEXT:    lvx 3, 0, 3
-; NOVSX-NEXT:    vaddudm 2, 2, 3
+; NOVSX-NEXT:    vsubudm 2, 2, 3
 ; NOVSX-NEXT:    blr
   %result = add <2 x i64> %x, <i64 1, i64 1>
   ret <2 x i64> %result