@@ -441,19 +441,18 @@ def XeVM_MemfenceOp
441441 }];
442442}
443443
444- def XeVM_PrefetchOp : XeVM_Op<"prefetch"> {
444+ def XeVM_PrefetchOp
445+ : XeVM_Op<"prefetch">,
446+ Arguments<(ins Arg<AnyTypeOf<[LLVM_PointerInAddressSpace<1>,
447+ LLVM_PointerInAddressSpace<4>]>>:$ptr,
448+ OptionalAttr<XeVM_LoadCacheControlAttr>:$cache_control)> {
445449 let summary = "Prefetch data into a cache subsystem.";
446450 let description = [{
447451 Work-item issues a prefetch from global memory to cache:
448452 * `ptr` - LLVM pointer with address space. Address space must be 1 (global)
449453 or 4 (generic)
450454 * `cache_control` - specify caching options
451455 }];
452-
453- let arguments = (ins AnyTypeOf<[LLVM_PointerInAddressSpace<1>,
454- LLVM_PointerInAddressSpace<4>]>:$ptr,
455- OptionalAttr<XeVM_LoadCacheControlAttr>:$cache_control);
456-
457456 let assemblyFormat = [{
458457 operands prop-dict attr-dict `:` `(` type(operands) `)`
459458 }];
@@ -462,7 +461,13 @@ def XeVM_PrefetchOp : XeVM_Op<"prefetch"> {
462461 }];
463462}
464463
465- def XeVM_BlockPrefetch2dOp : XeVM_Op<"blockprefetch2d"> {
464+ def XeVM_BlockPrefetch2dOp
465+ : XeVM_Op<"blockprefetch2d">,
466+ Arguments<(ins LLVM_AnyPointer:$ptr, I32:$base_width,
467+ I32:$base_height, I32:$base_pitch, I32:$x, I32:$y,
468+ I32Attr:$elem_size_in_bits, I32Attr:$tile_width, I32Attr:$tile_height,
469+ I32Attr:$v_blocks,
470+ OptionalAttr<XeVM_LoadCacheControlAttr>:$cache_control)> {
466471
467472 let summary = "2D block prefetch";
468473
@@ -492,11 +497,6 @@ def XeVM_BlockPrefetch2dOp : XeVM_Op<"blockprefetch2d"> {
492497 ```
493498 }];
494499
495- let arguments = (ins LLVM_AnyPointer:$ptr, I32:$base_width, I32:$base_height,
496- I32:$base_pitch, I32:$x, I32:$y, I32Attr:$elem_size_in_bits,
497- I32Attr:$tile_width, I32Attr:$tile_height, I32Attr:$v_blocks,
498- OptionalAttr<XeVM_LoadCacheControlAttr>:$cache_control);
499-
500500 let assemblyFormat = [{
501501 operands prop-dict attr-dict `:` `(` type(operands) `)`
502502 }];
0 commit comments