[AArch64] Regenerate and update a number of check lines. NFC

Author: davemgreen

llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll

@@ -35,8 +35,8 @@ define <8 x i16> @rhaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
 define <8 x i16> @hadds_zext(<8 x i8> %a0, <8 x i8> %a1) {
 ; CHECK-LABEL: hadds_zext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    uhadd   v0.8b, v0.8b, v1.8b
-; CHECK-NEXT:    ushll   v0.8h, v0.8b, #0
+; CHECK-NEXT:    uhadd v0.8b, v0.8b, v1.8b
+; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
 ; CHECK-NEXT:    ret
   %x0 = zext <8 x i8> %a0 to <8 x i16>
   %x1 = zext <8 x i8> %a1 to <8 x i16>

llvm/test/CodeGen/AArch64/aarch64-mulv.ll

@@ -2,7 +2,7 @@
 ; RUN: llc -mtriple=aarch64 -aarch64-enable-sink-fold=true -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
 ; RUN: llc -mtriple=aarch64 -aarch64-enable-sink-fold=true -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
-; CHECK_GI:        warning: Instruction selection used fallback path for mulv_v3i64
+; CHECK-GI:       warning: Instruction selection used fallback path for mulv_v3i32
 
 declare i8 @llvm.vector.reduce.mul.v2i8(<2 x i8>)
 declare i8 @llvm.vector.reduce.mul.v3i8(<3 x i8>)

llvm/test/CodeGen/AArch64/arm64-fp-contract-zero.ll

@@ -7,7 +7,7 @@
 define double @test_fms_fold(double %a, double %b) {
 ; CHECK-LABEL: test_fms_fold:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    movi {{d[0-9]+}}, #0000000000000000
+; CHECK-NEXT:    movi d0, #0000000000000000
 ; CHECK-NEXT:    ret
   %mul = fmul fast double %a, 0.000000e+00
   %mul1 = fmul fast double %b, 0.000000e+00

llvm/test/CodeGen/AArch64/arm64-neon-copy.ll

@@ -4,6 +4,8 @@
 
 ; CHECK-GI:       warning: Instruction selection used fallback path for test_bitcastv2f32tov1f64
 ; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_bitcastv1f64tov2f32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_concat_v1i32_undef
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_concat_diff_v1i32_v1i32
 
 define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
 ; CHECK-LABEL: ins16bw:

llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll

@@ -2,12 +2,12 @@
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
-; Test efficient codegen of vector extends up from legal type to 128 bit
-; and 256 bit vector types.
-
 ; CHECK-GI:       warning: Instruction selection used fallback path for zext_v32i1
 ; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for zext_v64i1
 
+; Test efficient codegen of vector extends up from legal type to 128 bit
+; and 256 bit vector types.
+
 ;-----
 ; Vectors of i16.
 ;-----

llvm/test/CodeGen/AArch64/arm64-vadd.ll

@@ -2,8 +2,8 @@
 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-SD
 ; RUN: llc < %s -mtriple=arm64-eabi -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
-; CHECK-GI:         warning: Instruction selection used fallback path for saddlp1d
-; CHECK-GI-NEXT:    warning: Instruction selection used fallback path for uaddlp1d
+; CHECK-GI:       warning: Instruction selection used fallback path for saddlp1d
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uaddlp1d
 
 define <8 x i8> @addhn8b(ptr %A, ptr %B) nounwind {
 ; CHECK-LABEL: addhn8b:

llvm/test/CodeGen/AArch64/arm64-vmul.ll

@@ -39,6 +39,7 @@
 ; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqdmlsl_d
 ; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_pmull_64
 ; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_pmull_high_64
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_commutable_pmull_64
 
 define <8 x i16> @smull8h(ptr %A, ptr %B) nounwind {
 ; CHECK-LABEL: smull8h:

llvm/test/CodeGen/AArch64/call-rv-marker.ll

@@ -139,16 +139,16 @@ define dso_local void @rv_marker_3() personality ptr @__gxx_personality_v0 {
 ; SELDAG-NEXT:    mov x29, x29
 ; SELDAG-NEXT:    bl _objc_retainAutoreleasedReturnValue
 ; SELDAG-NEXT:    mov x19, x0
-; SELDAG-NEXT:  Ltmp0:
+; SELDAG-NEXT:  Ltmp0: ; EH_LABEL
 ; SELDAG-NEXT:    bl _objc_object
-; SELDAG-NEXT:  Ltmp1:
+; SELDAG-NEXT:  Ltmp1: ; EH_LABEL
 ; SELDAG-NEXT:  ; %bb.1: ; %invoke.cont
 ; SELDAG-NEXT:    ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
 ; SELDAG-NEXT:    mov x0, x19
 ; SELDAG-NEXT:    ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
 ; SELDAG-NEXT:    b _objc_release
 ; SELDAG-NEXT:  LBB3_2: ; %lpad
-; SELDAG-NEXT:  Ltmp2:
+; SELDAG-NEXT:  Ltmp2: ; EH_LABEL
 ; SELDAG-NEXT:    mov x20, x0
 ; SELDAG-NEXT:    mov x0, x19
 ; SELDAG-NEXT:    bl _objc_release
@@ -197,9 +197,9 @@ define dso_local void @rv_marker_3() personality ptr @__gxx_personality_v0 {
 ; GISEL-NEXT:    mov x29, x29
 ; GISEL-NEXT:    bl _objc_retainAutoreleasedReturnValue
 ; GISEL-NEXT:    mov x19, x0
-; GISEL-NEXT:  Ltmp0:
+; GISEL-NEXT:  Ltmp0: ; EH_LABEL
 ; GISEL-NEXT:    bl _objc_object
-; GISEL-NEXT:  Ltmp1:
+; GISEL-NEXT:  Ltmp1: ; EH_LABEL
 ; GISEL-NEXT:  ; %bb.1: ; %invoke.cont
 ; GISEL-NEXT:  Lloh0:
 ; GISEL-NEXT:    adrp x1, _objc_release@GOTPAGE
@@ -210,7 +210,7 @@ define dso_local void @rv_marker_3() personality ptr @__gxx_personality_v0 {
 ; GISEL-NEXT:    ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
 ; GISEL-NEXT:    br x1
 ; GISEL-NEXT:  LBB3_2: ; %lpad
-; GISEL-NEXT:  Ltmp2:
+; GISEL-NEXT:  Ltmp2: ; EH_LABEL
 ; GISEL-NEXT:  Lloh2:
 ; GISEL-NEXT:    adrp x8, _objc_release@GOTPAGE
 ; GISEL-NEXT:    mov x20, x0
@@ -278,16 +278,16 @@ define dso_local void @rv_marker_4() personality ptr @__gxx_personality_v0 {
 ; SELDAG-NEXT:    .cfi_offset w29, -16
 ; SELDAG-NEXT:    .cfi_offset w19, -24
 ; SELDAG-NEXT:    .cfi_offset w20, -32
-; SELDAG-NEXT:  Ltmp3:
+; SELDAG-NEXT:  Ltmp3: ; EH_LABEL
 ; SELDAG-NEXT:    bl _foo1
 ; SELDAG-NEXT:    mov x29, x29
 ; SELDAG-NEXT:    bl _objc_retainAutoreleasedReturnValue
-; SELDAG-NEXT:  Ltmp4:
+; SELDAG-NEXT:  Ltmp4: ; EH_LABEL
 ; SELDAG-NEXT:  ; %bb.1: ; %invoke.cont
-; SELDAG-NEXT:  Ltmp6:
+; SELDAG-NEXT:  Ltmp6: ; EH_LABEL
 ; SELDAG-NEXT:    mov x19, x0
 ; SELDAG-NEXT:    bl _objc_object
-; SELDAG-NEXT:  Ltmp7:
+; SELDAG-NEXT:  Ltmp7: ; EH_LABEL
 ; SELDAG-NEXT:  ; %bb.2: ; %invoke.cont2
 ; SELDAG-NEXT:    mov x0, x19
 ; SELDAG-NEXT:    bl _objc_release
@@ -298,13 +298,13 @@ define dso_local void @rv_marker_4() personality ptr @__gxx_personality_v0 {
 ; SELDAG-NEXT:    add sp, sp, #48
 ; SELDAG-NEXT:    ret
 ; SELDAG-NEXT:  LBB4_3: ; %lpad1
-; SELDAG-NEXT:  Ltmp8:
+; SELDAG-NEXT:  Ltmp8: ; EH_LABEL
 ; SELDAG-NEXT:    mov x20, x0
 ; SELDAG-NEXT:    mov x0, x19
 ; SELDAG-NEXT:    bl _objc_release
 ; SELDAG-NEXT:    b LBB4_5
 ; SELDAG-NEXT:  LBB4_4: ; %lpad
-; SELDAG-NEXT:  Ltmp5:
+; SELDAG-NEXT:  Ltmp5: ; EH_LABEL
 ; SELDAG-NEXT:    mov x20, x0
 ; SELDAG-NEXT:  LBB4_5: ; %ehcleanup
 ; SELDAG-NEXT:    add x0, sp, #15
@@ -351,16 +351,16 @@ define dso_local void @rv_marker_4() personality ptr @__gxx_personality_v0 {
 ; GISEL-NEXT:    .cfi_offset w29, -16
 ; GISEL-NEXT:    .cfi_offset w19, -24
 ; GISEL-NEXT:    .cfi_offset w20, -32
-; GISEL-NEXT:  Ltmp3:
+; GISEL-NEXT:  Ltmp3: ; EH_LABEL
 ; GISEL-NEXT:    bl _foo1
 ; GISEL-NEXT:    mov x29, x29
 ; GISEL-NEXT:    bl _objc_retainAutoreleasedReturnValue
-; GISEL-NEXT:  Ltmp4:
+; GISEL-NEXT:  Ltmp4: ; EH_LABEL
 ; GISEL-NEXT:  ; %bb.1: ; %invoke.cont
-; GISEL-NEXT:  Ltmp6:
+; GISEL-NEXT:  Ltmp6: ; EH_LABEL
 ; GISEL-NEXT:    mov x19, x0
 ; GISEL-NEXT:    bl _objc_object
-; GISEL-NEXT:  Ltmp7:
+; GISEL-NEXT:  Ltmp7: ; EH_LABEL
 ; GISEL-NEXT:  ; %bb.2: ; %invoke.cont2
 ; GISEL-NEXT:  Lloh4:
 ; GISEL-NEXT:    adrp x8, _objc_release@GOTPAGE
@@ -375,7 +375,7 @@ define dso_local void @rv_marker_4() personality ptr @__gxx_personality_v0 {
 ; GISEL-NEXT:    add sp, sp, #48
 ; GISEL-NEXT:    ret
 ; GISEL-NEXT:  LBB4_3: ; %lpad1
-; GISEL-NEXT:  Ltmp8:
+; GISEL-NEXT:  Ltmp8: ; EH_LABEL
 ; GISEL-NEXT:  Lloh6:
 ; GISEL-NEXT:    adrp x8, _objc_release@GOTPAGE
 ; GISEL-NEXT:    mov x20, x0
@@ -385,7 +385,7 @@ define dso_local void @rv_marker_4() personality ptr @__gxx_personality_v0 {
 ; GISEL-NEXT:    blr x8
 ; GISEL-NEXT:    b LBB4_5
 ; GISEL-NEXT:  LBB4_4: ; %lpad
-; GISEL-NEXT:  Ltmp5:
+; GISEL-NEXT:  Ltmp5: ; EH_LABEL
 ; GISEL-NEXT:    mov x20, x0
 ; GISEL-NEXT:  LBB4_5: ; %ehcleanup
 ; GISEL-NEXT:    add x0, sp, #15

llvm/test/CodeGen/AArch64/callbr-prepare.ll

@@ -6,13 +6,13 @@ define i32 @test0() {
 ; CHECK-LABEL: @test0(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[OUT:%.*]] = callbr i32 asm "# $0", "=r,!i"()
-; CHECK-NEXT:    to label [[DIRECT:%.*]] [label %entry.indirect_crit_edge]
+; CHECK-NEXT:            to label [[DIRECT:%.*]] [label %entry.indirect_crit_edge]
 ; CHECK:       entry.indirect_crit_edge:
 ; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[OUT]])
 ; CHECK-NEXT:    br label [[INDIRECT:%.*]]
 ; CHECK:       direct:
 ; CHECK-NEXT:    [[OUT2:%.*]] = callbr i32 asm "# $0", "=r,!i"()
-; CHECK-NEXT:    to label [[DIRECT2:%.*]] [label %direct.indirect_crit_edge]
+; CHECK-NEXT:            to label [[DIRECT2:%.*]] [label %direct.indirect_crit_edge]
 ; CHECK:       direct.indirect_crit_edge:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[OUT2]])
 ; CHECK-NEXT:    br label [[INDIRECT]]
@@ -42,7 +42,7 @@ define i32 @dont_split0() {
 ; CHECK-LABEL: @dont_split0(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    callbr void asm "", "!i"()
-; CHECK-NEXT:    to label [[X:%.*]] [label %y]
+; CHECK-NEXT:            to label [[X:%.*]] [label %y]
 ; CHECK:       x:
 ; CHECK-NEXT:    ret i32 42
 ; CHECK:       y:
@@ -68,7 +68,7 @@ define i32 @dont_split1() {
 ; CHECK-LABEL: @dont_split1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT:    to label [[X:%.*]] [label %y]
+; CHECK-NEXT:            to label [[X:%.*]] [label %y]
 ; CHECK:       x:
 ; CHECK-NEXT:    ret i32 42
 ; CHECK:       y:
@@ -93,7 +93,7 @@ define i32 @dont_split2() {
 ; CHECK-LABEL: @dont_split2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    callbr void asm "", "!i"()
-; CHECK-NEXT:    to label [[X:%.*]] [label %y]
+; CHECK-NEXT:            to label [[X:%.*]] [label %y]
 ; CHECK:       x:
 ; CHECK-NEXT:    br label [[Y:%.*]]
 ; CHECK:       y:
@@ -119,7 +119,7 @@ define i32 @dont_split3() {
 ; CHECK-LABEL: @dont_split3(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT:    to label [[X:%.*]] [label %v]
+; CHECK-NEXT:            to label [[X:%.*]] [label %v]
 ; CHECK:       x:
 ; CHECK-NEXT:    br label [[V:%.*]]
 ; CHECK:       v:
@@ -142,7 +142,7 @@ define i32 @split_me0() {
 ; CHECK-LABEL: @split_me0(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT:    to label [[X:%.*]] [label %entry.y_crit_edge]
+; CHECK-NEXT:            to label [[X:%.*]] [label %entry.y_crit_edge]
 ; CHECK:       entry.y_crit_edge:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[Y:%.*]]
@@ -173,7 +173,7 @@ define i32 @split_me1(i1 %z) {
 ; CHECK-NEXT:    br i1 [[Z:%.*]], label [[W:%.*]], label [[V:%.*]]
 ; CHECK:       w:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i,!i"()
-; CHECK-NEXT:    to label [[X:%.*]] [label [[W_V_CRIT_EDGE:%.*]], label %w.v_crit_edge]
+; CHECK-NEXT:            to label [[X:%.*]] [label [[W_V_CRIT_EDGE:%.*]], label %w.v_crit_edge]
 ; CHECK:       w.v_crit_edge:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[V]]
@@ -206,7 +206,7 @@ define i32 @split_me2(i1 %z) {
 ; CHECK-NEXT:    br i1 [[Z:%.*]], label [[W:%.*]], label [[V:%.*]]
 ; CHECK:       w:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i,!i"()
-; CHECK-NEXT:    to label [[X:%.*]] [label [[W_V_CRIT_EDGE:%.*]], label %w.v_crit_edge]
+; CHECK-NEXT:            to label [[X:%.*]] [label [[W_V_CRIT_EDGE:%.*]], label %w.v_crit_edge]
 ; CHECK:       w.v_crit_edge:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[V]]
@@ -236,7 +236,7 @@ define i32 @dont_split4() {
 ; CHECK-LABEL: @dont_split4(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT:    to label [[X:%.*]] [label %y]
+; CHECK-NEXT:            to label [[X:%.*]] [label %y]
 ; CHECK:       x:
 ; CHECK-NEXT:    br label [[OUT:%.*]]
 ; CHECK:       y:
@@ -265,7 +265,7 @@ define i32 @dont_split5() {
 ; CHECK-LABEL: @dont_split5(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT:    to label [[OUT:%.*]] [label %y]
+; CHECK-NEXT:            to label [[OUT:%.*]] [label %y]
 ; CHECK:       y:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[OUT]]
@@ -289,7 +289,7 @@ define i32 @split_me3() {
 ; CHECK-LABEL: @split_me3(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT:    to label [[Y:%.*]] [label %entry.out_crit_edge]
+; CHECK-NEXT:            to label [[Y:%.*]] [label %entry.out_crit_edge]
 ; CHECK:       entry.out_crit_edge:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[OUT:%.*]]
@@ -318,7 +318,7 @@ define i32 @dont_split6(i32 %0) {
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[TMP1:%.*]] = phi i32 [ [[TMP0:%.*]], [[ENTRY:%.*]] ], [ [[TMP3:%.*]], [[LOOP_LOOP_CRIT_EDGE:%.*]] ]
 ; CHECK-NEXT:    [[TMP2:%.*]] = callbr i32 asm "", "=r,0,!i"(i32 [[TMP1]])
-; CHECK-NEXT:    to label [[EXIT:%.*]] [label %loop.loop_crit_edge]
+; CHECK-NEXT:            to label [[EXIT:%.*]] [label %loop.loop_crit_edge]
 ; CHECK:       loop.loop_crit_edge:
 ; CHECK-NEXT:    [[TMP3]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP2]])
 ; CHECK-NEXT:    br label [[LOOP]]
@@ -339,7 +339,7 @@ define i32 @split_me4() {
 ; CHECK-LABEL: @split_me4(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT:    to label [[SAME:%.*]] [label %entry.same_crit_edge]
+; CHECK-NEXT:            to label [[SAME:%.*]] [label %entry.same_crit_edge]
 ; CHECK:       entry.same_crit_edge:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[SAME]]
@@ -358,7 +358,7 @@ define i32 @split_me5() {
 ; CHECK-LABEL: @split_me5(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT:    to label [[SAME:%.*]] [label %entry.same_crit_edge]
+; CHECK-NEXT:            to label [[SAME:%.*]] [label %entry.same_crit_edge]
 ; CHECK:       entry.same_crit_edge:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.callbr.landingpad.i32(i32 [[TMP0]])
 ; CHECK-NEXT:    br label [[SAME]]
@@ -379,13 +379,13 @@ define i64 @split_me6() {
 ; CHECK-LABEL: @split_me6(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i64 asm "# $0 $1", "={dx},!i"()
-; CHECK-NEXT:    to label [[ASM_FALLTHROUGH:%.*]] [label %entry.foo_crit_edge]
+; CHECK-NEXT:            to label [[ASM_FALLTHROUGH:%.*]] [label %entry.foo_crit_edge]
 ; CHECK:       entry.foo_crit_edge:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.callbr.landingpad.i64(i64 [[TMP0]])
 ; CHECK-NEXT:    br label [[FOO:%.*]]
 ; CHECK:       asm.fallthrough:
 ; CHECK-NEXT:    [[TMP2:%.*]] = callbr i64 asm "# $0 $1", "={bx},!i"()
-; CHECK-NEXT:    to label [[FOO]] [label %asm.fallthrough.foo_crit_edge]
+; CHECK-NEXT:            to label [[FOO]] [label %asm.fallthrough.foo_crit_edge]
 ; CHECK:       asm.fallthrough.foo_crit_edge:
 ; CHECK-NEXT:    [[TMP3:%.*]] = call i64 @llvm.callbr.landingpad.i64(i64 [[TMP2]])
 ; CHECK-NEXT:    br label [[FOO]]
@@ -412,7 +412,7 @@ define i32 @multiple_split() {
 ; CHECK-LABEL: @multiple_split(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = callbr i32 asm "", "=r,!i"()
-; CHECK-NEXT:    to label [[X:%.*]] [label %y]
+; CHECK-NEXT:            to label [[X:%.*]] [label %y]
 ; CHECK:       x:
 ; CHECK-NEXT:    ret i32 42
 ; CHECK:       y:

llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll

@@ -1,16 +1,14 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16,+sve -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16,+sve2 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s --global-isel --global-isel-abort=2 --mattr=+complxnum,+neon,+fullfp16 -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; RUN: llc < %s --global-isel --global-isel-abort=2 --mattr=+complxnum,+neon,+fullfp16,+sve -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; RUN: llc < %s --global-isel --global-isel-abort=2 --mattr=+complxnum,+neon,+fullfp16,+sve2 -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-
-target triple = "aarch64"
-
-; CHECK-GI:      warning: Instruction selection used fallback path for complex_add_v16f16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for complex_add_v32f16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for complex_add_v16f16_with_intrinsic
+; RUN: llc < %s -mtriple=aarch64 --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 --mattr=+complxnum,+neon,+fullfp16,+sve -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 --mattr=+complxnum,+neon,+fullfp16,+sve2 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 --global-isel --global-isel-abort=2 --mattr=+complxnum,+neon,+fullfp16 -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc < %s -mtriple=aarch64 --global-isel --global-isel-abort=2 --mattr=+complxnum,+neon,+fullfp16,+sve -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc < %s -mtriple=aarch64 --global-isel --global-isel-abort=2 --mattr=+complxnum,+neon,+fullfp16,+sve2 -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI:       warning: Instruction selection used fallback path for complex_add_v16f16
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for complex_add_v32f16
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for complex_add_v16f16_with_intrinsic
 
 ; Expected to not transform
 define <2 x half> @complex_add_v2f16(<2 x half> %a, <2 x half> %b) {