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Author: gandhi56

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

@@ -2984,36 +2984,35 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
       // Fallback: If we need an SGPR but cannot scavenge one and there is no
       // frame register, try to convert the flat-scratch instruction to use a
       // VGPR index (SS -> SV) and materialize the offset in a VGPR.
-      if (!TmpSReg && !FrameReg && TII->isFLATScratch(*MI)) {
+      unsigned Opc = MI->getOpcode();
+      int NewOpc = AMDGPU::getFlatScratchInstSVfromSS(Opc);
+      if (!TmpSReg && !FrameReg && TII->isFLATScratch(*MI) && NewOpc != -1) {
         // Reuse an existing VGPR temp if available, otherwise scavenge one.
         Register VTmp = (!UseSGPR && TmpReg)
                             ? TmpReg
                             : RS->scavengeRegisterBackwards(
-                                  AMDGPU::VGPR_32RegClass, MI, false, 0);
+                                  AMDGPU::VGPR_32RegClass, MI,
+                                  /*RestoreAfter=*/false, /*SPAdj=*/0);
         if (VTmp) {
           // Put the large offset into a VGPR and zero the immediate offset.
           BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), VTmp)
               .addImm(Offset);
 
-          unsigned Opc = MI->getOpcode();
-          int NewOpc = AMDGPU::getFlatScratchInstSVfromSS(Opc);
-          if (NewOpc != -1) {
-            int OldSAddrIdx =
-                AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr);
-            int NewVAddrIdx =
-                AMDGPU::getNamedOperandIdx(NewOpc, AMDGPU::OpName::vaddr);
-            if (OldSAddrIdx == NewVAddrIdx && OldSAddrIdx >= 0) {
-              MI->setDesc(TII->get(NewOpc));
-              // Replace former saddr (now vaddr) with the VGPR index.
-              MI->getOperand(NewVAddrIdx).ChangeToRegister(VTmp, false);
-              // Reset the immediate offset to 0 as it is now in vaddr.
-              MachineOperand *OffOp =
-                  TII->getNamedOperand(*MI, AMDGPU::OpName::offset);
-              assert(OffOp && "Flat scratch SV form must have offset operand");
-              OffOp->setImm(0);
-              return false;
-            }
-          }
+          int OldSAddrIdx =
+              AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr);
+          int NewVAddrIdx =
+              AMDGPU::getNamedOperandIdx(NewOpc, AMDGPU::OpName::vaddr);
+
+          assert(OldSAddrIdx >= 0 && NewVAddrIdx >= 0 &&
+                 "Invalid address operand indexes");
+          MI->setDesc(TII->get(NewOpc));
+          MI->getOperand(NewVAddrIdx).ChangeToRegister(VTmp, false);
+          MachineOperand *OffOp =
+              TII->getNamedOperand(*MI, AMDGPU::OpName::offset);
+
+          assert(OffOp && "Flat scratch SV form must have offset operand");
+          OffOp->setImm(0);
+          return false;
         }
       }