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[RISCV] Support target attribute for function
The proposal of target attribute is riscv-non-isa/riscv-c-api-doc#35 This patch implements it by emitting .option arch during codegen. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D151730
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6 files changed

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‎clang/include/clang/Basic/DiagnosticSemaKinds.td‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3177,6 +3177,10 @@ def warn_unsupported_target_attribute
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def err_attribute_unsupported
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: Error<"%0 attribute is not supported on targets missing %1;"
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" specify an appropriate -march= or -mcpu=">;
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def err_duplicate_target_attribute
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: Error<"%select{unsupported|duplicate|unknown}0%select{| CPU|"
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" tune CPU}1 '%2' in the '%select{target|target_clones|target_version}3' "
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"attribute string; ">;
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// The err_*_attribute_argument_not_int are separate because they're used by
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// VerifyIntegerConstantExpression.
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def err_aligned_attribute_argument_not_int : Error<

‎clang/lib/Basic/Targets/RISCV.cpp‎

Lines changed: 125 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -235,6 +235,47 @@ ArrayRef<Builtin::Info> RISCVTargetInfo::getTargetBuiltins() const {
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clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin);
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}
237237

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static std::vector<std::string>
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collectNonISAExtFeature(const std::vector<std::string> &FeaturesNeedOverride,
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int XLen) {
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auto ParseResult =
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llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesNeedOverride);
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if (!ParseResult) {
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consumeError(ParseResult.takeError());
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return std::vector<std::string>();
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}
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std::vector<std::string> ImpliedFeatures = (*ParseResult)->toFeatureVector();
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std::vector<std::string> NonISAExtFeatureVec;
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llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
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[&](const std::string &Feat) {
255+
return !llvm::is_contained(ImpliedFeatures, Feat);
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});
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return NonISAExtFeatureVec;
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}
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static std::vector<std::string>
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resolveTargetAttrOverride(const std::vector<std::string> &FeaturesVec,
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int XLen) {
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auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
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if (I == FeaturesVec.end())
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return FeaturesVec;
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const std::vector<std::string> FeaturesNeedOverride(FeaturesVec.begin(), I);
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std::vector<std::string> NonISAExtFeature =
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collectNonISAExtFeature(FeaturesNeedOverride, XLen);
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auto ResolvedFeature = std::vector(++I, FeaturesVec.end());
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ResolvedFeature.insert(ResolvedFeature.end(), NonISAExtFeature.begin(),
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NonISAExtFeature.end());
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return ResolvedFeature;
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}
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238279
bool RISCVTargetInfo::initFeatureMap(
239280
llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
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const std::vector<std::string> &FeaturesVec) const {
@@ -248,7 +289,10 @@ bool RISCVTargetInfo::initFeatureMap(
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Features["32bit"] = true;
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}
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251-
auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
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std::vector<std::string> NewFeaturesVec =
293+
resolveTargetAttrOverride(FeaturesVec, XLen);
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auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
252296
if (!ParseResult) {
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std::string Buffer;
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llvm::raw_string_ostream OutputErrMsg(Buffer);
@@ -262,7 +306,7 @@ bool RISCVTargetInfo::initFeatureMap(
262306
// RISCVISAInfo makes implications for ISA features
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std::vector<std::string> ImpliedFeatures = (*ParseResult)->toFeatureVector();
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// Add non-ISA features like `relax` and `save-restore` back
265-
for (const std::string &Feature : FeaturesVec)
309+
for (const std::string &Feature : NewFeaturesVec)
266310
if (!llvm::is_contained(ImpliedFeatures, Feature))
267311
ImpliedFeatures.push_back(Feature);
268312

@@ -359,3 +403,82 @@ void RISCVTargetInfo::fillValidTuneCPUList(
359403
bool Is64Bit = getTriple().isArch64Bit();
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llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
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}
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static void handleFullArchString(StringRef FullArchStr,
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std::vector<std::string> &Features) {
409+
Features.push_back("__RISCV_TargetAttrNeedOverride");
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auto RII = llvm::RISCVISAInfo::parseArchString(
411+
FullArchStr, /* EnableExperimentalExtension */ true);
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if (!RII) {
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consumeError(RII.takeError());
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// Forward the invalid FullArchStr.
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Features.push_back("+" + FullArchStr.str());
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} else {
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std::vector<std::string> FeatStrings = (*RII)->toFeatureVector();
418+
for (auto FeatString : FeatStrings)
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Features.push_back(FeatString);
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}
421+
}
422+
423+
ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
424+
ParsedTargetAttr Ret;
425+
if (Features == "default")
426+
return Ret;
427+
SmallVector<StringRef, 1> AttrFeatures;
428+
Features.split(AttrFeatures, ";");
429+
bool FoundArch = false;
430+
431+
for (auto &Feature : AttrFeatures) {
432+
Feature = Feature.trim();
433+
StringRef AttrString = Feature.split("=").second.trim();
434+
435+
if (Feature.startswith("arch=")) {
436+
// Override last features
437+
Ret.Features.clear();
438+
if (FoundArch)
439+
Ret.Duplicate = "arch=";
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FoundArch = true;
441+
442+
if (AttrString.startswith("+")) {
443+
// EXTENSION like arch=+v,+zbb
444+
SmallVector<StringRef, 1> Exts;
445+
AttrString.split(Exts, ",");
446+
for (auto Ext : Exts) {
447+
if (Ext.empty())
448+
continue;
449+
450+
StringRef ExtName = Ext.substr(1);
451+
std::string TargetFeature =
452+
llvm::RISCVISAInfo::getTargetFeatureForExtension(ExtName);
453+
if (!TargetFeature.empty())
454+
Ret.Features.push_back(Ext.front() + TargetFeature);
455+
else
456+
Ret.Features.push_back(Ext.str());
457+
}
458+
} else {
459+
// full-arch-string like arch=rv64gcv
460+
handleFullArchString(AttrString, Ret.Features);
461+
}
462+
} else if (Feature.startswith("cpu=")) {
463+
if (!Ret.CPU.empty())
464+
Ret.Duplicate = "cpu=";
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466+
Ret.CPU = AttrString;
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468+
if (!FoundArch) {
469+
// Update Features with CPU's features
470+
StringRef MarchFromCPU = llvm::RISCV::getMArchFromMcpu(Ret.CPU);
471+
if (MarchFromCPU != "") {
472+
Ret.Features.clear();
473+
handleFullArchString(MarchFromCPU, Ret.Features);
474+
}
475+
}
476+
} else if (Feature.startswith("tune=")) {
477+
if (!Ret.Tune.empty())
478+
Ret.Duplicate = "tune=";
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Ret.Tune = AttrString;
481+
}
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}
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return Ret;
484+
}

‎clang/lib/Basic/Targets/RISCV.h‎

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@@ -117,6 +117,8 @@ class RISCVTargetInfo : public TargetInfo {
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
118118
bool isValidTuneCPUName(StringRef Name) const override;
119119
void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
120+
bool supportsTargetAttributeTune() const override { return true; }
121+
ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
120122
};
121123
class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
122124
public:

‎clang/lib/Sema/SemaDeclAttr.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3451,6 +3451,11 @@ bool Sema::checkTargetAttr(SourceLocation LiteralLoc, StringRef AttrStr) {
34513451
return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
34523452
<< Unknown << Tune << ParsedAttrs.Tune << Target;
34533453

3454+
if (Context.getTargetInfo().getTriple().isRISCV() &&
3455+
ParsedAttrs.Duplicate != "")
3456+
return Diag(LiteralLoc, diag::err_duplicate_target_attribute)
3457+
<< Duplicate << None << ParsedAttrs.Duplicate << Target;
3458+
34543459
if (ParsedAttrs.Duplicate != "")
34553460
return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
34563461
<< Duplicate << None << ParsedAttrs.Duplicate << Target;

‎clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
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// REQUIRES: riscv-registered-target
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// RUN: not %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m -target-feature +a \
3+
// RUN: -emit-llvm %s 2>&1 | FileCheck %s
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5+
// CHECK: error: duplicate 'arch=' in the 'target' attribute string;
6+
__attribute__((target("arch=rv64gc;arch=rv64gc_zbb"))) void testMultiArchSelectLast() {}
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// CHECK: error: duplicate 'cpu=' in the 'target' attribute string;
8+
__attribute__((target("cpu=sifive-u74;cpu=sifive-u54"))) void testMultiCpuSelectLast() {}
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// CHECK: error: duplicate 'tune=' in the 'target' attribute string;
10+
__attribute__((target("tune=sifive-u74;tune=sifive-u54"))) void testMultiTuneSelectLast() {}

‎clang/test/CodeGen/RISCV/riscv-func-attr-target.c‎

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
// REQUIRES: riscv-registered-target
2+
// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m \
3+
// RUN: -target-feature +a -target-feature +save-restore \
4+
// RUN: -emit-llvm %s -o - | FileCheck %s
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6+
// CHECK-LABEL: define dso_local void @testDefault
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// CHECK-SAME: () #0 {
8+
void testDefault() {}
9+
// CHECK-LABEL: define dso_local void @testMultiAttrStr
10+
// CHECK-SAME: () #1 {
11+
__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void
12+
testMultiAttrStr() {}
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// CHECK-LABEL: define dso_local void @testSingleExtension
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// CHECK-SAME: () #2 {
15+
__attribute__((target("arch=+zbb"))) void testSingleExtension() {}
16+
// CHECK-LABEL: define dso_local void @testMultiExtension
17+
// CHECK-SAME: () #3 {
18+
__attribute__((target("arch=+zbb,+v,+zicond"))) void testMultiExtension() {}
19+
// CHECK-LABEL: define dso_local void @testFullArch
20+
// CHECK-SAME: () #4 {
21+
__attribute__((target("arch=rv64gc_zbb"))) void testFullArch() {}
22+
// CHECK-LABEL: define dso_local void @testFullArchButSmallThanCmdArch
23+
// CHECK-SAME: () #5 {
24+
__attribute__((target("arch=rv64im"))) void testFullArchButSmallThanCmdArch() {}
25+
// CHECK-LABEL: define dso_local void @testAttrArchAndAttrCpu
26+
// CHECK-SAME: () #6 {
27+
__attribute__((target("cpu=sifive-u54;arch=+zbb"))) void
28+
testAttrArchAndAttrCpu() {}
29+
// CHECK-LABEL: define dso_local void @testAttrFullArchAndAttrCpu
30+
// CHECK-SAME: () #7 {
31+
__attribute__((target("cpu=sifive-u54;arch=rv64im"))) void
32+
testAttrFullArchAndAttrCpu() {}
33+
// CHECK-LABEL: define dso_local void @testAttrCpuOnly
34+
// CHECK-SAME: () #8 {
35+
__attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
36+
37+
//.
38+
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei" }
39+
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" "tune-cpu"="generic-rv64" }
40+
// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei" }
41+
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
42+
// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei" }
43+
// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore" }
44+
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei" }
45+
// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore" }
46+
// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei" }

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