Move restriction to the default implementation of isDesirableToCommuteWithShift for targets

Author: LiqinWeng

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -4305,6 +4305,12 @@ class TargetLowering : public TargetLoweringBase {
   /// @param Level the current DAGCombine legalization level.
   virtual bool isDesirableToCommuteWithShift(const SDNode *N,
                                              CombineLevel Level) const {
+    SDValue ShiftLHS = N->getOperand(0);
+    if (!ShiftLHS->hasOneUse())
+      return false;
+    if (ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
+        !ShiftLHS.getOperand(0)->hasOneUse())
+      return false;
     return true;
   }
 

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

@@ -2152,24 +2152,6 @@ bool HexagonTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
   return X.getValueType().isScalarInteger(); // 'tstbit'
 }
 
-bool HexagonTargetLowering::isDesirableToCommuteWithShift(
-    const SDNode *N, CombineLevel Level) const {
-  assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
-          N->getOpcode() == ISD::SRL) &&
-         "Expected shift op");
-
-  SDValue ShiftLHS = N->getOperand(0);
-
-  if (!ShiftLHS->hasOneUse())
-    return false;
-
-  if (ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
-      !ShiftLHS.getOperand(0)->hasOneUse())
-    return false;
-
-  return true;
-}
-
 bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
   return isTruncateFree(EVT::getEVT(Ty1), EVT::getEVT(Ty2));
 }

llvm/lib/Target/Hexagon/HexagonISelLowering.h

@@ -155,9 +155,6 @@ class HexagonTargetLowering : public TargetLowering {
 
   bool hasBitTest(SDValue X, SDValue Y) const override;
 
-  bool isDesirableToCommuteWithShift(const SDNode *N,
-                                     CombineLevel Level) const override;
-
   bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
 
   /// Return true if an FMA operation is faster than a pair of mul and add

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -19166,20 +19166,3 @@ Value *PPCTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
   return Builder.CreateOr(
       Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
 }
-
-bool PPCTargetLowering::isDesirableToCommuteWithShift(
-    const SDNode *N, CombineLevel Level) const {
-  assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
-          N->getOpcode() == ISD::SRL) &&
-         "Expected shift op");
-
-  SDValue ShiftLHS = N->getOperand(0);
-  if (!ShiftLHS->hasOneUse())
-    return false;
-
-  if (ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
-      !ShiftLHS.getOperand(0)->hasOneUse())
-    return false;
-
-  return true;
-}

llvm/lib/Target/PowerPC/PPCISelLowering.h

@@ -1497,9 +1497,6 @@ namespace llvm {
     /// through to determine the optimal load/store instruction format.
     unsigned computeMOFlags(const SDNode *Parent, SDValue N,
                             SelectionDAG &DAG) const;
-
-    bool isDesirableToCommuteWithShift(const SDNode *N,
-                                       CombineLevel Level) const override;
   }; // end class PPCTargetLowering
 
   namespace PPC {

llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll

@@ -32,9 +32,9 @@ define void @add_sext_shl_moreOneUse_addexceedsign12(ptr %array1, i32 %a, i32 %b
 ; RV64-LABEL: add_sext_shl_moreOneUse_addexceedsign12:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi a3, a1, 2047
-; RV64-NEXT:    addi a3, a3, 1
 ; RV64-NEXT:    lui a4, 2
 ; RV64-NEXT:    sext.w a1, a1
+; RV64-NEXT:    addi a3, a3, 1
 ; RV64-NEXT:    slli a1, a1, 2
 ; RV64-NEXT:    add a0, a0, a4
 ; RV64-NEXT:    add a0, a0, a1
@@ -121,19 +121,19 @@ define void @add_sext_shl_moreOneUse_add_inSelect_addexceedsign12(ptr %array1, i
 ; RV64-LABEL: add_sext_shl_moreOneUse_add_inSelect_addexceedsign12:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi a4, a1, 2047
-; RV64-NEXT:    addi a4, a4, 1
 ; RV64-NEXT:    lui a5, 2
-; RV64-NEXT:    slli a1, a1, 2
-; RV64-NEXT:    add a0, a0, a1
+; RV64-NEXT:    slli a6, a1, 2
+; RV64-NEXT:    addi a1, a4, 1
+; RV64-NEXT:    add a0, a0, a6
 ; RV64-NEXT:    add a0, a0, a5
-; RV64-NEXT:    mv a1, a4
+; RV64-NEXT:    mv a4, a1
 ; RV64-NEXT:    bgtz a3, .LBB4_2
 ; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    mv a1, a2
+; RV64-NEXT:    mv a4, a2
 ; RV64-NEXT:  .LBB4_2: # %entry
-; RV64-NEXT:    sw a1, 0(a0)
-; RV64-NEXT:    sw a1, 4(a0)
-; RV64-NEXT:    sw a4, 120(a0)
+; RV64-NEXT:    sw a4, 0(a0)
+; RV64-NEXT:    sw a4, 4(a0)
+; RV64-NEXT:    sw a1, 120(a0)
 ; RV64-NEXT:    ret
 entry:
   %add = add nsw i32 %a, 2048

llvm/test/CodeGen/RISCV/add_shl_constant.ll

@@ -40,9 +40,9 @@ define void @add_shl_moreOneUse_inStore_addexceedsign12(ptr %array1, i32 %a, i32
 ; RV32-LABEL: add_shl_moreOneUse_inStore_addexceedsign12:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    addi a3, a1, 2047
-; RV32-NEXT:    addi a3, a3, 1
 ; RV32-NEXT:    lui a4, 2
 ; RV32-NEXT:    slli a1, a1, 2
+; RV32-NEXT:    addi a3, a3, 1
 ; RV32-NEXT:    add a0, a0, a1
 ; RV32-NEXT:    add a0, a0, a4
 ; RV32-NEXT:    sw a2, 0(a0)