[AMDGPU][NFC] Reduce diff between downstream branch (#155779)

Author: mariusz-sikora-at-amd

llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h

@@ -74,10 +74,10 @@ class AMDGPUMachineModuleInfo final : public MachineModuleInfoELF {
   /// otherwise
   bool isOneAddressSpace(SyncScope::ID SSID) const {
     return SSID == getSingleThreadOneAddressSpaceSSID() ||
-        SSID == getWavefrontOneAddressSpaceSSID() ||
-        SSID == getWorkgroupOneAddressSpaceSSID() ||
-        SSID == getAgentOneAddressSpaceSSID() ||
-        SSID == getSystemOneAddressSpaceSSID();
+           SSID == getWavefrontOneAddressSpaceSSID() ||
+           SSID == getWorkgroupOneAddressSpaceSSID() ||
+           SSID == getAgentOneAddressSpaceSSID() ||
+           SSID == getSystemOneAddressSpaceSSID();
   }
 
 public:

llvm/lib/Target/AMDGPU/SIISelLowering.h

@@ -14,8 +14,8 @@
 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
 
-#include "AMDGPUISelLowering.h"
 #include "AMDGPUArgumentUsageInfo.h"
+#include "AMDGPUISelLowering.h"
 #include "llvm/CodeGen/MachineFunction.h"
 
 namespace llvm {

llvm/lib/Target/AMDGPU/SIInstrInfo.td

@@ -1806,15 +1806,15 @@ class getVALUDstForVT<ValueType VT, bit IsTrue16 = 0, bit IsVOP3Encoding = 0> {
                                    VOPDstOperand_t16Lo128),
                     VOPDstOperand<VGPR_32>);
   RegisterOperand ret = !cond(!eq(VT.Size, 1024) : VOPDstOperand<VReg_1024>,
-                              !eq(VT.Size, 512) : VOPDstOperand<VReg_512>,
-                              !eq(VT.Size, 256) : VOPDstOperand<VReg_256>,
-                              !eq(VT.Size, 192) : VOPDstOperand<VReg_192>,
-                              !eq(VT.Size, 128) : VOPDstOperand<VReg_128>,
+                              !eq(VT.Size, 512)  : VOPDstOperand<VReg_512>,
+                              !eq(VT.Size, 256)  : VOPDstOperand<VReg_256>,
+                              !eq(VT.Size, 192)  : VOPDstOperand<VReg_192>,
+                              !eq(VT.Size, 128)  : VOPDstOperand<VReg_128>,
                               !eq(VT.Size, 96)   : VOPDstOperand<VReg_96>,
-                              !eq(VT.Size, 64)  : VOPDstOperand<VReg_64>,
-                              !eq(VT.Size, 32)  : VOPDstOperand<VGPR_32>,
-                              !eq(VT.Size, 16)  : op16,
-                              1                 : VOPDstS64orS32); // else VT == i1
+                              !eq(VT.Size, 64)   : VOPDstOperand<VReg_64>,
+                              !eq(VT.Size, 32)   : VOPDstOperand<VGPR_32>,
+                              !eq(VT.Size, 16)   : op16,
+                              1                  : VOPDstS64orS32); // else VT == i1
 }
 
 class getVALUDstForVT_fake16<ValueType VT> {

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

@@ -1249,15 +1249,15 @@ class SrcReg9<RegisterClass regClass> : RegisterOperand<regClass> {
   let DecoderMethod = "decodeSrcReg9<" # regClass.Size # ">";
 }
 
-def VRegSrc_32 : SrcReg9<VGPR_32>;
-def VRegSrc_64 : SrcReg9<VReg_64>;
-def VRegSrc_96 : SrcReg9<VReg_96>;
-def VRegSrc_128: SrcReg9<VReg_128>;
-def VRegSrc_192: SrcReg9<VReg_192>;
-def VRegSrc_256: SrcReg9<VReg_256>;
-def VRegSrc_384: SrcReg9<VReg_384>;
-def VRegSrc_512: SrcReg9<VReg_512>;
-def VRegSrc_1024: SrcReg9<VReg_1024>;
+def VRegSrc_32   : SrcReg9<VGPR_32>;
+def VRegSrc_64   : SrcReg9<VReg_64>;
+def VRegSrc_96   : SrcReg9<VReg_96>;
+def VRegSrc_128  : SrcReg9<VReg_128>;
+def VRegSrc_192  : SrcReg9<VReg_192>;
+def VRegSrc_256  : SrcReg9<VReg_256>;
+def VRegSrc_384  : SrcReg9<VReg_384>;
+def VRegSrc_512  : SrcReg9<VReg_512>;
+def VRegSrc_1024 : SrcReg9<VReg_1024>;
 def VRegOrLdsSrc_32 : SrcReg9<VRegOrLds_32>;
 
 // True 16 Operands