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mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td

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@@ -29,14 +29,14 @@ def XeGPUSubgroupDistribute : Pass<"xegpu-subgroup-distribute"> {
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"vector::VectorDialect"];
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}
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def XeGPULayoutPropagate : Pass<"xegpu-layout-propagate"> {
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def XeGPULayoutPropagate : Pass<"xegpu-propagate-layout"> {
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let summary = "Propagate and assign XeGPU layout information";
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let description = [{
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This pass propagates the XeGPU layout information accross ops. Starting
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from a set of anchor operations (e.g. `dpas`, `store_nd`), this will
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propagate the layouts required for their operands to the producers. With
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this propagated layout information, pass will then update the XeGPU tensor
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descriptor type with the layout information.
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this propagated layout information, pass will then update op result type
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with the layout information.
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}];
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let dependentDialects = ["memref::MemRefDialect", "xegpu::XeGPUDialect",
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"vector::VectorDialect"];

mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutPropagate.cpp

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@@ -44,7 +44,7 @@ namespace xegpu {
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} // namespace xegpu
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} // namespace mlir
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#define DEBUG_TYPE "xegpu-layout-propagate"
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#define DEBUG_TYPE "xegpu-propagate-layout"
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#define DBGS() (llvm::dbgs() << "[" DEBUG_TYPE "]: ")
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using namespace mlir;

mlir/test/Dialect/XeGPU/layout-propagate.mlir renamed to mlir/test/Dialect/XeGPU/propagate-layout.mlir

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@@ -1,4 +1,4 @@
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// RUN: mlir-opt -xegpu-layout-propagate -split-input-file %s | FileCheck %s
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// RUN: mlir-opt -xegpu-propagate-layout -split-input-file %s | FileCheck %s
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// CHECK-LABEL: func.func @dpas_f16(
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// CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: memref<8x16xf16>, %[[ARG1:[0-9a-zA-Z]+]]: memref<16x16xf16>, %[[ARG2:[0-9a-zA-Z]+]]: memref<8x16xf32>) {

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