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adam-yangadam-yang
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More cleanup
1 parent 78ab7f3 commit d8b6711

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7 files changed

+175
-173
lines changed

7 files changed

+175
-173
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUHotBlockRematerialize.cpp‎

Lines changed: 37 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -2308,7 +2308,7 @@ void applySubExpCloneNearUser(SubExp &Exp, std::vector<HotBlock> &HotBlocks,
23082308
}
23092309
// Build dag for SubExp to help remove unused inst when clone.
23102310
ExpDag Dag(MRI, SIRI, SIII, /*IsJoinInput*/ true);
2311-
Dag.build(Exp.inputLive, Exp.outputLive, Exp.SUnits);
2311+
Dag.build(Exp.InputLive, Exp.OutputLive, Exp.SUnits);
23122312
DenseSet<SUnit *> DagBottoms;
23132313
for (SUnit &SU : Dag.SUnits) {
23142314
if (!SU.isInstr())
@@ -3141,10 +3141,10 @@ bool tryRemat(MachineBasicBlock &MBB, MachineInstr *HotMi,
31413141
if (SubExp.IsNotSafeToCopy)
31423142
continue;
31433143
if (IsVGPR) {
3144-
if (SubExp.vOutputSize == 0)
3144+
if (SubExp.VOutputSize == 0)
31453145
continue;
31463146
} else {
3147-
if (SubExp.sOutputSize == 0)
3147+
if (SubExp.SOutputSize == 0)
31483148
continue;
31493149
}
31503150
if (!SubExp.isSafeToMove(MRI, /*IsMoveUp*/ false))
@@ -3158,9 +3158,9 @@ bool tryRemat(MachineBasicBlock &MBB, MachineInstr *HotMi,
31583158
if (SubExp.IsHasMemInst && MemWriteMBBSet.count(&MBB))
31593159
continue;
31603160
if (IsVGPR) {
3161-
Distance -= SubExp.vOutputSize;
3161+
Distance -= SubExp.VOutputSize;
31623162
} else {
3163-
Distance -= SubExp.sOutputSize;
3163+
Distance -= SubExp.SOutputSize;
31643164
}
31653165
CloneSubExps.emplace_back(SubExp);
31663166
if (Distance <= 0)
@@ -3256,8 +3256,8 @@ bool tryRematInHotSpot(
32563256
// When apply subExp1 before subExp0, new clone of subExp0 which use result of
32573257
// subExp1 will have old reg of subExp1. And reg pressure will not be reduced.
32583258
void sortSubExpCandidates(std::vector<SubExp> &SubExpCandidates) {
3259-
MapVector<unsigned, SetVector<SubExp *>> InputMap;
3260-
MapVector<unsigned, SetVector<SubExp *>> OutputMap;
3259+
MapVector<Register, SetVector<SubExp *>> InputMap;
3260+
MapVector<Register, SetVector<SubExp *>> OutputMap;
32613261
struct SortNode {
32623262
SubExp Exp;
32633263
unsigned Depth;
@@ -3288,7 +3288,7 @@ void sortSubExpCandidates(std::vector<SubExp> &SubExpCandidates) {
32883288
MapVector<SubExp *, SortNode> SortMap;
32893289
for (auto It : InputMap) {
32903290
unsigned Reg = It.first;
3291-
auto OutIt = OutputMap.find(Reg);
3291+
MapVector<Register, SetVector<SubExp *>>::iterator OutIt = OutputMap.find(Reg);
32923292
if (OutIt == OutputMap.end())
32933293
continue;
32943294
auto &InExps = It.second;
@@ -3302,8 +3302,8 @@ void sortSubExpCandidates(std::vector<SubExp> &SubExpCandidates) {
33023302
continue;
33033303
// Canot input(use) move up, output(def) move down.
33043304
// Choose the exp which save more.
3305-
int InExpGain = InExp->vOutputSize - InExp->vInputSize;
3306-
int OutExpGain = OutExp->vInputSize - InExp->vOutputSize;
3305+
int InExpGain = InExp->VOutputSize - InExp->VInputSize;
3306+
int OutExpGain = OutExp->VInputSize - InExp->VOutputSize;
33073307
if (InExpGain >= OutExpGain) {
33083308
OutExp->SUnits.clear();
33093309
} else {
@@ -3415,26 +3415,26 @@ bool canHelpPressureWhenSink(SubExp &SubExp,
34153415

34163416
// Update input size to ignore lives in which already in
34173417
// passThrus.
3418-
for (auto It : SubExp.inputLive) {
3418+
for (auto It : SubExp.InputLive) {
34193419
unsigned Reg = It.first;
34203420
if (PassThrus.count(Reg) == 0)
34213421
continue;
34223422
unsigned Size = getRegSize(Reg, It.second, MRI, SIRI);
34233423
if (SIRI->isVGPR(MRI, Reg)) {
3424-
SubExp.vInputSize -= Size;
3424+
SubExp.VInputSize -= Size;
34253425
} else {
3426-
SubExp.sInputSize -= Size;
3426+
SubExp.SInputSize -= Size;
34273427
}
34283428
}
34293429

3430-
if (SubExp.vInputSize > SubExp.vOutputSize)
3430+
if (SubExp.VInputSize > SubExp.VOutputSize)
34313431
return false;
34323432

3433-
if (SubExp.sInputSize > SubExp.sOutputSize && IsSgprBound)
3433+
if (SubExp.SInputSize > SubExp.SOutputSize && IsSgprBound)
34343434
return false;
34353435

3436-
if (SubExp.sInputSize >= SubExp.sOutputSize &&
3437-
SubExp.vInputSize == SubExp.vOutputSize)
3436+
if (SubExp.SInputSize >= SubExp.SOutputSize &&
3437+
SubExp.VInputSize == SubExp.VOutputSize)
34383438
return false;
34393439

34403440
// Try to find a Insert Block.
@@ -3479,13 +3479,13 @@ bool canHelpPressureWhenHoist(SubExp &SubExp, const MachineRegisterInfo &MRI,
34793479
const MachineLoopInfo *MLI, bool IsSgprBound) {
34803480
if (!SubExp.isSafeToMove(MRI, /*IsMoveUp*/ true))
34813481
return false;
3482-
if (SubExp.vInputSize < SubExp.vOutputSize)
3482+
if (SubExp.VInputSize < SubExp.VOutputSize)
34833483
return false;
3484-
if (SubExp.sInputSize < SubExp.sOutputSize && IsSgprBound)
3484+
if (SubExp.SInputSize < SubExp.SOutputSize && IsSgprBound)
34853485
return false;
34863486

3487-
if (SubExp.sInputSize <= SubExp.sOutputSize &&
3488-
SubExp.vInputSize == SubExp.vOutputSize)
3487+
if (SubExp.SInputSize <= SubExp.SOutputSize &&
3488+
SubExp.VInputSize == SubExp.VOutputSize)
34893489
return false;
34903490

34913491
// Try to find a Insert Block.
@@ -3715,17 +3715,17 @@ SubExp buildFreeSubExp(SubExp &Exp,
37153715

37163716
// Calc reg for freeExp.
37173717
for (unsigned Reg : FreeExp.TopRegs) {
3718-
FreeExp.inputLive[Reg];
3718+
FreeExp.InputLive[Reg];
37193719
}
37203720

37213721
for (unsigned Reg : FreeExp.BottomRegs) {
3722-
FreeExp.outputLive[Reg];
3722+
FreeExp.OutputLive[Reg];
37233723
}
37243724

3725-
CollectLiveSetPressure(FreeExp.inputLive, MRI, SIRI, FreeExp.vInputSize,
3726-
FreeExp.sInputSize);
3727-
CollectLiveSetPressure(FreeExp.outputLive, MRI, SIRI, FreeExp.vOutputSize,
3728-
FreeExp.sOutputSize);
3725+
CollectLiveSetPressure(FreeExp.InputLive, MRI, SIRI, FreeExp.VInputSize,
3726+
FreeExp.SInputSize);
3727+
CollectLiveSetPressure(FreeExp.OutputLive, MRI, SIRI, FreeExp.VOutputSize,
3728+
FreeExp.SOutputSize);
37293729
return FreeExp;
37303730
}
37313731

@@ -3817,14 +3817,14 @@ calculateSaving(HotBlock &HotBb, std::vector<SubExp> &SubExpCandidates,
38173817
continue;
38183818
// When subExp is from hotBB, check output instead of input.
38193819
if (Exp.FromBB == MBB) {
3820-
if (IsVOutBound && Exp.vOutputSize < Exp.vInputSize)
3820+
if (IsVOutBound && Exp.VOutputSize < Exp.VInputSize)
38213821
continue;
3822-
if (IsSOutBound && Exp.sOutputSize < Exp.sInputSize)
3822+
if (IsSOutBound && Exp.SOutputSize < Exp.SInputSize)
38233823
continue;
3824-
Vgpr += Exp.vInputSize;
3825-
Vgpr -= Exp.vOutputSize;
3826-
Sgpr += Exp.sInputSize;
3827-
Sgpr -= Exp.sOutputSize;
3824+
Vgpr += Exp.VInputSize;
3825+
Vgpr -= Exp.VOutputSize;
3826+
Sgpr += Exp.SInputSize;
3827+
Sgpr -= Exp.SOutputSize;
38283828
continue;
38293829
}
38303830
}
@@ -3852,7 +3852,7 @@ calculateSaving(HotBlock &HotBb, std::vector<SubExp> &SubExpCandidates,
38523852
}
38533853
}
38543854

3855-
for (auto OutIt : Exp.outputLive) {
3855+
for (auto OutIt : Exp.OutputLive) {
38563856
unsigned Reg = OutIt.first;
38573857
LaneBitmask OutMask = OutIt.second;
38583858
LaneBitmask MBBBeginMask;
@@ -3887,7 +3887,7 @@ calculateSaving(HotBlock &HotBb, std::vector<SubExp> &SubExpCandidates,
38873887
}
38883888
}
38893889

3890-
for (auto InIt : Exp.inputLive) {
3890+
for (auto InIt : Exp.InputLive) {
38913891
unsigned Reg = InIt.first;
38923892
LaneBitmask InMask = InIt.second;
38933893
LaneBitmask MBBBeginMask;
@@ -3929,7 +3929,7 @@ calculateSaving(HotBlock &HotBb, std::vector<SubExp> &SubExpCandidates,
39293929
// If MBB dominate any user of output live reg, It will still live in
39303930
// MBB. So cannot count that output live reg as profit.
39313931
// Hoist into loop is not supported now.
3932-
for (auto OutIt : Exp.outputLive) {
3932+
for (auto OutIt : Exp.OutputLive) {
39333933
unsigned Reg = OutIt.first;
39343934
bool IsDomUser = false;
39353935
for (MachineInstr &MI : MRI.use_nodbg_instructions(Reg)) {
@@ -3963,7 +3963,7 @@ calculateSaving(HotBlock &HotBb, std::vector<SubExp> &SubExpCandidates,
39633963
}
39643964
}
39653965

3966-
for (auto InIt : Exp.inputLive) {
3966+
for (auto InIt : Exp.InputLive) {
39673967
unsigned Reg = InIt.first;
39683968
LaneBitmask InMask = InIt.second;
39693969
LaneBitmask MBBBeginMask;

‎llvm/lib/Target/AMDGPU/AMDGPUMIRUtils.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -453,7 +453,7 @@ bool reduceChannel(unsigned offset, MachineInstr &MI, const MCInstrDesc &desc,
453453
.addImm(offset * LaneSize);
454454
MachineInstr *OffsetAddMI = OffsetAdd.getInstr();
455455
MachineBasicBlock::iterator InsertPoint =
456-
llvm::FindOrCreateInsertionPointForSccDef(MI.getParent(), MI, SIRI,
456+
llvm::findOrCreateInsertionPointForSccDef(MI.getParent(), MI, SIRI,
457457
SIII, &MRI);
458458
MI.getParent()->insert(InsertPoint, OffsetAddMI);
459459
SIII->legalizeOperands(*OffsetAddMI);

‎llvm/lib/Target/AMDGPU/AMDGPUMIRUtils.h‎

Lines changed: 22 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,6 @@
1+
#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMIRUTILS_H
2+
#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMIRUTILS_H
3+
14
#pragma once
25

36
#include "llvm/ADT/DenseMap.h"
@@ -37,14 +40,14 @@ using LiveSet = llvm::DenseMap<unsigned, llvm::LaneBitmask>;
3740
unsigned getRegSize(unsigned Reg, llvm::LaneBitmask &Mask,
3841
const llvm::MachineRegisterInfo &MRI,
3942
const llvm::SIRegisterInfo *SIRI);
40-
void CollectLiveSetPressure(const LiveSet &liveSet,
43+
void collectLiveSetPressure(const LiveSet &liveSet,
4144
const llvm::MachineRegisterInfo &MRI,
4245
const llvm::SIRegisterInfo *SIRI,
4346
unsigned &VPressure, unsigned &SPressure);
4447

4548
bool isExecUpdateForControlFlow(llvm::MachineInstr &MI);
4649

47-
bool IsSub0Sub1SingleDef(unsigned Reg, const llvm::MachineRegisterInfo &MRI);
50+
bool isSub0Sub1SingleDef(unsigned Reg, const llvm::MachineRegisterInfo &MRI);
4851

4952
llvm::LaneBitmask getRegMask(const llvm::MachineOperand &MO,
5053
const llvm::MachineRegisterInfo &MRI);
@@ -68,40 +71,40 @@ bool reach_block(llvm::MachineBasicBlock *FromBB,
6871
void viewCFGWithPhi(llvm::MachineFunction &MF);
6972
void write_contribution_list(llvm::MachineFunction &MF, const char *Filename);
7073

71-
llvm::MachineBasicBlock *CreateNullExportBlock(llvm::MachineFunction &MF,
74+
llvm::MachineBasicBlock *createNullExportBlock(llvm::MachineFunction &MF,
7275
const llvm::SIInstrInfo *TII);
7376

74-
bool GetNonDebugMBBEnd(llvm::MachineBasicBlock::reverse_iterator &BBEnd,
77+
bool getNonDebugMBBEnd(llvm::MachineBasicBlock::reverse_iterator &BBEnd,
7578
llvm::MachineBasicBlock &MBB);
7679

77-
void UpdatePhysRegLiveInForBlock(llvm::MachineBasicBlock *NewBB,
80+
void updatePhysRegLiveInForBlock(llvm::MachineBasicBlock *NewBB,
7881
const llvm::MachineRegisterInfo *MRI);
7982

80-
void BuildPhysRegLiveInForBlock(llvm::MachineBasicBlock *NewBB,
83+
void buildPhysRegLiveInForBlock(llvm::MachineBasicBlock *NewBB,
8184
llvm::SmallDenseSet<unsigned, 8> &LiveOutSet,
8285
const llvm::MachineRegisterInfo *MRI);
8386

84-
MachineReg CreateVirtualRegForOperand(MachineOpcode Opcode, unsigned Operand,
87+
MachineReg createVirtualRegForOperand(MachineOpcode Opcode, unsigned Operand,
8588
llvm::MachineFunction &MF);
8689

87-
MachineReg CreateVirtualDstReg(MachineOpcode Opcode, llvm::MachineFunction &MF);
90+
MachineReg createVirtualDstReg(MachineOpcode Opcode, llvm::MachineFunction &MF);
8891

89-
bool IsExecCopy(const llvm::MachineInstr &MI, MachineReg Exec,
92+
bool isExecCopy(const llvm::MachineInstr &MI, MachineReg Exec,
9093
MachineReg *pDst);
9194
struct MachineRegWithSubReg {
9295
MachineReg Reg = /*NoRegister*/ 0;
9396
unsigned SubReg = /*NoSubRegister*/ 0;
9497
};
95-
MachineRegWithSubReg GetWqmEntryActiveMask(llvm::MachineFunction &MF);
96-
llvm::MachineInstr *GetWqmEntryActiveMaskInst(llvm::MachineFunction &MF);
98+
MachineRegWithSubReg getWqmEntryActiveMask(llvm::MachineFunction &MF);
99+
llvm::MachineInstr *getWqmEntryActiveMaskInst(llvm::MachineFunction &MF);
97100

98101
// Return true if this machine instruction represents a call to the fetch
99102
// shader. We curently have two mechanisims for calling fetch shader:
100103
// 1. The AMDGPU_CALL_FETCH_SHADER pseudo-instruction
101104
// 2. A CALL instruction with the `FetchShaderCall` flag set to true.
102-
bool IsFetchShaderCall(const llvm::MachineInstr *MI);
105+
bool isFetchShaderCall(const llvm::MachineInstr *MI);
103106

104-
bool IsSccLiveAt(llvm::MachineBasicBlock *MBB,
107+
bool isSccLiveAt(llvm::MachineBasicBlock *MBB,
105108
llvm::MachineBasicBlock::iterator MI);
106109

107110
// An enum used to pass additional constraints to
@@ -126,7 +129,7 @@ enum SccDefInsertPointConstraintFlags {
126129
// scc around BeforeInst. This way BeforeInst can safely be used
127130
// as the new insert location.
128131
//
129-
llvm::MachineBasicBlock::iterator FindOrCreateInsertionPointForSccDef(
132+
llvm::MachineBasicBlock::iterator findOrCreateInsertionPointForSccDef(
130133
llvm::MachineBasicBlock *MBB, llvm::MachineBasicBlock::iterator BeforeInst,
131134
const llvm::TargetRegisterInfo *TRI, const llvm::SIInstrInfo *TII,
132135
llvm::MachineRegisterInfo *MRI,
@@ -149,9 +152,9 @@ void buildEndLiveMap(
149152

150153
void dumpLiveSet(const LiveSet &LiveSet, const llvm::SIRegisterInfo *SIRI);
151154

152-
unsigned GetCurrentVGPRCount(llvm::MachineFunction &MF,
155+
unsigned getCurrentVGPRCount(llvm::MachineFunction &MF,
153156
const llvm::SIRegisterInfo *SIRI);
154-
unsigned GetCurrentSGPRCount(llvm::MachineFunction &MF,
157+
unsigned getCurrentSGPRCount(llvm::MachineFunction &MF,
155158
const llvm::SIRegisterInfo *SIRI);
156159

157160
bool isFastMathInst(llvm::MachineInstr &MI);
@@ -169,7 +172,7 @@ void write_pressure(llvm::MachineFunction &MF, llvm::LiveIntervals *LIS,
169172
// Look for the successor `Succ` of the given `MBB`.
170173
// Returns MBB->succ_end() if `Succ` is not a successor of MBB.
171174
llvm::MachineBasicBlock::succ_iterator
172-
FindSuccessor(llvm::MachineBasicBlock *MBB, llvm::MachineBasicBlock *Succ);
175+
findSuccessor(llvm::MachineBasicBlock *MBB, llvm::MachineBasicBlock *Succ);
173176

174177
// The enum and helper function for v_perm selection mask.
175178
//
@@ -210,3 +213,5 @@ constexpr int buildVPermSelectMask(V_PERM_IN_BYTE_POS Sel_0,
210213
(int)Sel_0);
211214
}
212215
} // namespace llvm
216+
217+
#endif

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