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Add tests
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‎llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll‎

Lines changed: 81 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,6 +131,85 @@ define <4 x i64> @interleave2_v4i64(<2 x i64> %vec0, <2 x i64> %vec1) {
131131
ret <4 x i64> %retval
132132
}
133133

134+
define <4 x i16> @interleave2_same_const_splat_v4i16() {
135+
; CHECK-SD-LABEL: interleave2_same_const_splat_v4i16:
136+
; CHECK-SD: // %bb.0:
137+
; CHECK-SD-NEXT: movi v0.4h, #3
138+
; CHECK-SD-NEXT: ret
139+
;
140+
; CHECK-GI-LABEL: interleave2_same_const_splat_v4i16:
141+
; CHECK-GI: // %bb.0:
142+
; CHECK-GI-NEXT: mov w8, #3 // =0x3
143+
; CHECK-GI-NEXT: fmov s0, w8
144+
; CHECK-GI-NEXT: mov v0.h[1], w8
145+
; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
146+
; CHECK-GI-NEXT: ret
147+
%retval = call <4 x i16> @llvm.vector.interleave2.v4i16(<2 x i16> splat(i16 3), <2 x i16> splat(i16 3))
148+
ret <4 x i16> %retval
149+
}
150+
151+
define <4 x i16> @interleave2_diff_const_splat_v4i16() {
152+
; CHECK-SD-LABEL: interleave2_diff_const_splat_v4i16:
153+
; CHECK-SD: // %bb.0:
154+
; CHECK-SD-NEXT: adrp x8, .LCPI11_0
155+
; CHECK-SD-NEXT: ldr d0, [x8, :lo12:.LCPI11_0]
156+
; CHECK-SD-NEXT: ret
157+
;
158+
; CHECK-GI-LABEL: interleave2_diff_const_splat_v4i16:
159+
; CHECK-GI: // %bb.0:
160+
; CHECK-GI-NEXT: mov w8, #3 // =0x3
161+
; CHECK-GI-NEXT: mov w9, #4 // =0x4
162+
; CHECK-GI-NEXT: fmov s0, w8
163+
; CHECK-GI-NEXT: fmov s1, w9
164+
; CHECK-GI-NEXT: mov v0.h[1], w8
165+
; CHECK-GI-NEXT: mov v1.h[1], w9
166+
; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v1.4h
167+
; CHECK-GI-NEXT: ret
168+
%retval = call <4 x i16> @llvm.vector.interleave2.v4i16(<2 x i16> splat(i16 3), <2 x i16> splat(i16 4))
169+
ret <4 x i16> %retval
170+
}
171+
172+
define <4 x i16> @interleave2_same_nonconst_splat_v4i16(i16 %a) {
173+
; CHECK-SD-LABEL: interleave2_same_nonconst_splat_v4i16:
174+
; CHECK-SD: // %bb.0:
175+
; CHECK-SD-NEXT: dup v0.4h, w0
176+
; CHECK-SD-NEXT: ret
177+
;
178+
; CHECK-GI-LABEL: interleave2_same_nonconst_splat_v4i16:
179+
; CHECK-GI: // %bb.0:
180+
; CHECK-GI-NEXT: dup v0.4h, w0
181+
; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
182+
; CHECK-GI-NEXT: ret
183+
%ins = insertelement <2 x i16> poison, i16 %a, i32 0
184+
%splat = shufflevector <2 x i16> %ins, <2 x i16> poison, <2 x i32> <i32 0, i32 0>
185+
%retval = call <4 x i16> @llvm.vector.interleave2.v4i16(<2 x i16> %splat, <2 x i16> %splat)
186+
ret <4 x i16> %retval
187+
}
188+
189+
define <4 x i16> @interleave2_diff_nonconst_splat_v4i16(i16 %a, i16 %b) {
190+
; CHECK-SD-LABEL: interleave2_diff_nonconst_splat_v4i16:
191+
; CHECK-SD: // %bb.0:
192+
; CHECK-SD-NEXT: fmov s0, w0
193+
; CHECK-SD-NEXT: mov v0.h[1], w0
194+
; CHECK-SD-NEXT: mov v0.h[2], w1
195+
; CHECK-SD-NEXT: mov v0.h[3], w1
196+
; CHECK-SD-NEXT: rev32 v1.4h, v0.4h
197+
; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v1.4h
198+
; CHECK-SD-NEXT: ret
199+
;
200+
; CHECK-GI-LABEL: interleave2_diff_nonconst_splat_v4i16:
201+
; CHECK-GI: // %bb.0:
202+
; CHECK-GI-NEXT: dup v0.4h, w0
203+
; CHECK-GI-NEXT: dup v1.4h, w1
204+
; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v1.4h
205+
; CHECK-GI-NEXT: ret
206+
%ins1 = insertelement <2 x i16> poison, i16 %a, i32 0
207+
%splat1 = shufflevector <2 x i16> %ins1, <2 x i16> poison, <2 x i32> <i32 0, i32 0>
208+
%ins2 = insertelement <2 x i16> poison, i16 %b, i32 0
209+
%splat2 = shufflevector <2 x i16> %ins2, <2 x i16> poison, <2 x i32> <i32 0, i32 0>
210+
%retval = call <4 x i16> @llvm.vector.interleave2.v4i16(<2 x i16> %splat1, <2 x i16> %splat2)
211+
ret <4 x i16> %retval
212+
}
134213

135214
; Float declarations
136215
declare <4 x half> @llvm.vector.interleave2.v4f16(<2 x half>, <2 x half>)
@@ -145,4 +224,5 @@ declare <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8>, <16 x i8>)
145224
declare <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16>, <8 x i16>)
146225
declare <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32>, <4 x i32>)
147226
declare <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64>, <2 x i64>)
148-
227+
declare <4 x i16> @llvm.vector.interleave2.v4i16(<2 x i16>, <2 x i16>)
228+
declare <8 x i16> @llvm.vector.interleave4.v8i16(<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>)

‎llvm/test/CodeGen/AArch64/sve-vector-interleave.ll‎

Lines changed: 169 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -267,7 +267,7 @@ define <vscale x 32 x i16> @interleave4_nxv8i16(<vscale x 8 x i16> %vec0, <vscal
267267
; SME2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
268268
; SME2-NEXT: zip { z0.h - z3.h }, { z0.h - z3.h }
269269
; SME2-NEXT: ret
270-
%retval = call <vscale x 32 x i16> @llvm.vector.interleave4.nxv8i16(<vscale x 8 x i16> %vec0, <vscale x 8 x i16> %vec1, <vscale x 8 x i16> %vec2, <vscale x 8 x i16> %vec3)
270+
%retval = call <vscale x 32 x i16> @llvm.vector.interleave4.nxv32i16(<vscale x 8 x i16> %vec0, <vscale x 8 x i16> %vec1, <vscale x 8 x i16> %vec2, <vscale x 8 x i16> %vec3)
271271
ret <vscale x 32 x i16> %retval
272272
}
273273

@@ -540,6 +540,172 @@ define <vscale x 4 x i32> @interleave2_nxv2i32(<vscale x 2 x i32> %vec0, <vscale
540540
ret <vscale x 4 x i32> %retval
541541
}
542542

543+
define <vscale x 4 x i16> @interleave2_same_const_splat_nxv4i16() {
544+
; SVE-LABEL: interleave2_same_const_splat_nxv4i16:
545+
; SVE: // %bb.0:
546+
; SVE-NEXT: mov z0.d, #3 // =0x3
547+
; SVE-NEXT: zip2 z1.d, z0.d, z0.d
548+
; SVE-NEXT: zip1 z0.d, z0.d, z0.d
549+
; SVE-NEXT: uzp1 z0.s, z0.s, z1.s
550+
; SVE-NEXT: ret
551+
;
552+
; SME2-LABEL: interleave2_same_const_splat_nxv4i16:
553+
; SME2: // %bb.0:
554+
; SME2-NEXT: mov z0.d, #3 // =0x3
555+
; SME2-NEXT: zip { z0.d, z1.d }, z0.d, z0.d
556+
; SME2-NEXT: uzp1 z0.s, z0.s, z1.s
557+
; SME2-NEXT: ret
558+
%retval = call <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 3))
559+
ret <vscale x 4 x i16> %retval
560+
}
561+
562+
define <vscale x 4 x i16> @interleave2_diff_const_splat_nxv4i16() {
563+
; SVE-LABEL: interleave2_diff_const_splat_nxv4i16:
564+
; SVE: // %bb.0:
565+
; SVE-NEXT: mov z0.d, #4 // =0x4
566+
; SVE-NEXT: mov z1.d, #3 // =0x3
567+
; SVE-NEXT: zip2 z2.d, z1.d, z0.d
568+
; SVE-NEXT: zip1 z0.d, z1.d, z0.d
569+
; SVE-NEXT: uzp1 z0.s, z0.s, z2.s
570+
; SVE-NEXT: ret
571+
;
572+
; SME2-LABEL: interleave2_diff_const_splat_nxv4i16:
573+
; SME2: // %bb.0:
574+
; SME2-NEXT: mov z0.d, #4 // =0x4
575+
; SME2-NEXT: mov z1.d, #3 // =0x3
576+
; SME2-NEXT: zip { z0.d, z1.d }, z1.d, z0.d
577+
; SME2-NEXT: uzp1 z0.s, z0.s, z1.s
578+
; SME2-NEXT: ret
579+
%retval = call <vscale x 4 x i16> @llvm.vector.interleave2.v4i16(<vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 4))
580+
ret <vscale x 4 x i16> %retval
581+
}
582+
583+
define <vscale x 4 x i16> @interleave2_same_nonconst_splat_nxv4i16(i16 %a) {
584+
; SVE-LABEL: interleave2_same_nonconst_splat_nxv4i16:
585+
; SVE: // %bb.0:
586+
; SVE-NEXT: // kill: def $w0 killed $w0 def $x0
587+
; SVE-NEXT: mov z0.d, x0
588+
; SVE-NEXT: zip2 z1.d, z0.d, z0.d
589+
; SVE-NEXT: zip1 z0.d, z0.d, z0.d
590+
; SVE-NEXT: uzp1 z0.s, z0.s, z1.s
591+
; SVE-NEXT: ret
592+
;
593+
; SME2-LABEL: interleave2_same_nonconst_splat_nxv4i16:
594+
; SME2: // %bb.0:
595+
; SME2-NEXT: // kill: def $w0 killed $w0 def $x0
596+
; SME2-NEXT: mov z0.d, x0
597+
; SME2-NEXT: zip { z0.d, z1.d }, z0.d, z0.d
598+
; SME2-NEXT: uzp1 z0.s, z0.s, z1.s
599+
; SME2-NEXT: ret
600+
%ins = insertelement <vscale x 2 x i16> poison, i16 %a, i32 0
601+
%splat = shufflevector <vscale x 2 x i16> %ins, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
602+
%retval = call <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16> %splat, <vscale x 2 x i16> %splat)
603+
ret <vscale x 4 x i16> %retval
604+
}
605+
606+
define <vscale x 4 x i16> @interleave2_diff_nonconst_splat_nxv4i16(i16 %a, i16 %b) {
607+
; SVE-LABEL: interleave2_diff_nonconst_splat_nxv4i16:
608+
; SVE: // %bb.0:
609+
; SVE-NEXT: // kill: def $w1 killed $w1 def $x1
610+
; SVE-NEXT: // kill: def $w0 killed $w0 def $x0
611+
; SVE-NEXT: mov z0.d, x0
612+
; SVE-NEXT: mov z1.d, x1
613+
; SVE-NEXT: zip2 z2.d, z0.d, z1.d
614+
; SVE-NEXT: zip1 z0.d, z0.d, z1.d
615+
; SVE-NEXT: uzp1 z0.s, z0.s, z2.s
616+
; SVE-NEXT: ret
617+
;
618+
; SME2-LABEL: interleave2_diff_nonconst_splat_nxv4i16:
619+
; SME2: // %bb.0:
620+
; SME2-NEXT: // kill: def $w1 killed $w1 def $x1
621+
; SME2-NEXT: // kill: def $w0 killed $w0 def $x0
622+
; SME2-NEXT: mov z0.d, x0
623+
; SME2-NEXT: mov z1.d, x1
624+
; SME2-NEXT: zip { z0.d, z1.d }, z0.d, z1.d
625+
; SME2-NEXT: uzp1 z0.s, z0.s, z1.s
626+
; SME2-NEXT: ret
627+
%ins1 = insertelement <vscale x 2 x i16> poison, i16 %a, i32 0
628+
%splat1 = shufflevector <vscale x 2 x i16> %ins1, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
629+
%ins2 = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
630+
%splat2 = shufflevector <vscale x 2 x i16> %ins2, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
631+
%retval = call <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16> %splat1, <vscale x 2 x i16> %splat2)
632+
ret <vscale x 4 x i16> %retval
633+
}
634+
635+
define <vscale x 8 x i16> @interleave4_same_const_splat_nxv8i16() {
636+
; SVE-LABEL: interleave4_same_const_splat_nxv8i16:
637+
; SVE: // %bb.0:
638+
; SVE-NEXT: mov z0.d, #3 // =0x3
639+
; SVE-NEXT: zip1 z1.d, z0.d, z0.d
640+
; SVE-NEXT: zip1 z2.d, z1.d, z1.d
641+
; SVE-NEXT: zip2 z1.d, z1.d, z1.d
642+
; SVE-NEXT: uzp1 z2.s, z2.s, z0.s
643+
; SVE-NEXT: uzp1 z2.h, z2.h, z0.h
644+
; SVE-NEXT: uunpklo z2.s, z2.h
645+
; SVE-NEXT: uunpklo z2.d, z2.s
646+
; SVE-NEXT: uzp1 z1.s, z2.s, z1.s
647+
; SVE-NEXT: uzp1 z2.h, z1.h, z0.h
648+
; SVE-NEXT: zip2 z0.d, z0.d, z0.d
649+
; SVE-NEXT: uunpkhi z2.s, z2.h
650+
; SVE-NEXT: zip1 z3.d, z0.d, z0.d
651+
; SVE-NEXT: zip2 z0.d, z0.d, z0.d
652+
; SVE-NEXT: uunpkhi z2.d, z2.s
653+
; SVE-NEXT: uzp1 z2.s, z3.s, z2.s
654+
; SVE-NEXT: uzp1 z2.h, z1.h, z2.h
655+
; SVE-NEXT: uunpkhi z2.s, z2.h
656+
; SVE-NEXT: uunpklo z2.d, z2.s
657+
; SVE-NEXT: uzp1 z0.s, z2.s, z0.s
658+
; SVE-NEXT: uzp1 z0.h, z1.h, z0.h
659+
; SVE-NEXT: ret
660+
;
661+
; SME-ALL-LABEL: interleave4_same_const_splat_nxv8i16:
662+
; SME-ALL: // %bb.0:
663+
; SME-ALL-NEXT: mov z0.d, #3 // =0x3
664+
; SME-ALL-NEXT: zip { z0.d, z1.d }, z0.d, z0.d
665+
; SME-ALL-NEXT: zip { z2.d, z3.d }, z0.d, z0.d
666+
; SME-ALL-NEXT: uzp1 z4.s, z2.s, z0.s
667+
; SME-ALL-NEXT: uzp1 z4.h, z4.h, z0.h
668+
; SME-ALL-NEXT: uunpklo z4.s, z4.h
669+
; SME-ALL-NEXT: uunpklo z4.d, z4.s
670+
; SME-ALL-NEXT: uzp1 z2.s, z4.s, z3.s
671+
; SME-ALL-NEXT: uzp1 z3.h, z2.h, z0.h
672+
; SME-ALL-NEXT: zip { z0.d, z1.d }, z1.d, z1.d
673+
; SME-ALL-NEXT: uunpkhi z3.s, z3.h
674+
; SME-ALL-NEXT: uunpkhi z3.d, z3.s
675+
; SME-ALL-NEXT: uzp1 z3.s, z0.s, z3.s
676+
; SME-ALL-NEXT: uzp1 z3.h, z2.h, z3.h
677+
; SME-ALL-NEXT: uunpkhi z3.s, z3.h
678+
; SME-ALL-NEXT: uunpklo z3.d, z3.s
679+
; SME-ALL-NEXT: uzp1 z0.s, z3.s, z1.s
680+
; SME-ALL-NEXT: uzp1 z0.h, z2.h, z0.h
681+
; SME-ALL-NEXT: ret
682+
;
683+
; SME2-256-LABEL: interleave4_same_const_splat_nxv8i16:
684+
; SME2-256: // %bb.0:
685+
; SME2-256-NEXT: mov z0.d, #3 // =0x3
686+
; SME2-256-NEXT: mov z1.d, z0.d
687+
; SME2-256-NEXT: mov z2.d, z0.d
688+
; SME2-256-NEXT: mov z3.d, z0.d
689+
; SME2-256-NEXT: zip { z0.d - z3.d }, { z0.d - z3.d }
690+
; SME2-256-NEXT: uzp1 z4.s, z0.s, z0.s
691+
; SME2-256-NEXT: uzp1 z4.h, z4.h, z0.h
692+
; SME2-256-NEXT: uunpklo z4.s, z4.h
693+
; SME2-256-NEXT: uunpklo z4.d, z4.s
694+
; SME2-256-NEXT: uzp1 z4.s, z4.s, z1.s
695+
; SME2-256-NEXT: uzp1 z5.h, z4.h, z0.h
696+
; SME2-256-NEXT: uunpkhi z5.s, z5.h
697+
; SME2-256-NEXT: uunpkhi z5.d, z5.s
698+
; SME2-256-NEXT: uzp1 z5.s, z2.s, z5.s
699+
; SME2-256-NEXT: uzp1 z5.h, z4.h, z5.h
700+
; SME2-256-NEXT: uunpkhi z5.s, z5.h
701+
; SME2-256-NEXT: uunpklo z5.d, z5.s
702+
; SME2-256-NEXT: uzp1 z0.s, z5.s, z3.s
703+
; SME2-256-NEXT: uzp1 z0.h, z4.h, z0.h
704+
; SME2-256-NEXT: ret
705+
%retval = call <vscale x 8 x i16> @llvm.vector.interleave4.nxv8i16(<vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 3))
706+
ret <vscale x 8 x i16> %retval
707+
}
708+
543709
; Float declarations
544710
declare <vscale x 4 x half> @llvm.vector.interleave2.nxv4f16(<vscale x 2 x half>, <vscale x 2 x half>)
545711
declare <vscale x 8 x half> @llvm.vector.interleave2.nxv8f16(<vscale x 4 x half>, <vscale x 4 x half>)
@@ -567,3 +733,5 @@ declare <vscale x 8 x i64> @llvm.vector.interleave2.nxv8i64(<vscale x 4 x i64>,
567733
declare <vscale x 16 x i8> @llvm.vector.interleave2.nxv16i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
568734
declare <vscale x 8 x i16> @llvm.vector.interleave2.nxv8i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
569735
declare <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
736+
declare <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
737+
declare <vscale x 8 x i16> @llvm.vector.interleave4.nxv8i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>)

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